VIVADO报错解决： logical ports have no user assigned specific location constraint (LOC)

今天第一次使用Xilinx的开发软件VIVADO 2015.2进行BASYS 3的开发，然后经历Synthesis ,  Implementation 之后的第三步骤Program and Debug中，在Generate Bitstream这个环节出现了错误，查看一下Log，发现了如下错误。

[Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 3 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. Problem ports: clk, din, dout.

Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 3 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. Problem ports: clk, din, dout.

解决方法：

按照红色提示：将  

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1] 

指令写入一个后缀名为 .tcl 的文件，然后点击Bitstream Settings，将这个.tcl文件添加作为一个tcl pre hook文件。

当然，如果引脚不是很多的话，可以直接在PinAssignment下拉菜单中选择合适的电平，即可。

图片如下: