硬件设计中的事实标准一 SPI标准 (de facto standard)

硬件设计中的事实标准一 SPI标准 (de facto standard)

原文链接: http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus

bluenochange 翻译

The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.

串行设备接口总线或SPI总线是由摩托罗拉公司（现在叫做飞思卡尔Freescale）命名的一种工作与全双工模式的同步数据通信标准。设备在主机或从机模式下通信，主机设备初始化数据帧。多个从机设备允许有各自独立的从机选择线（片选线）。有时区别于3线、2线和1线串口总线，SPI也被叫做4线串口总线。

Standards
The SPI bus is a sort of de facto standard, rather than one agreed by any international committee.

SPI总线也是一种事实标准，它没有被任何的国际委员会承认。

However, that lack of standardization is reflected in a wide variety of protocol options. Different word sizes are common. Every device defines its own protocol, including whether or not it supports commands at all. Some devices are transmit-only; others are receive-only. Chip selects are sometimes active-high rather than active-low. Some protocols send the least significant bit first.

但是，这种缺乏标准化的特点在协议选项的多样化中表现出来。不同的字长是很常见的。每个器件定义了它们自己的协议，包括它们是否支持命令。一些器件只能发送，另一些只能接受。片选有时是高有效而不是低有效。一些协议是先发送最低有效位的。

Some devices even have minor variances from the CPOL/CPHA modes described above. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response. Some devices have two clocks, one to "capture" or "display" data, and another to clock it into the device. Many of these "capture clocks" run from the chip select line.

一些器件甚至在CPOL/CPHA模式上与上面介绍的有微小的差异。数据从主机发给从机可能会使用与从机发给主机相反的时钟沿。设备通常在第一个时钟之前和最后一个时钟之后需要额外的空闲时钟时间，或者在一个命令和它的响应之间也需要。一些设备有两个时钟，一个用于“捕获”或者“显示”数据，另一个则用于提供将数据输入器件的时序。很多的“捕获时钟”脱离片选线运行。

Some devices require an additional flow control signal from slave to master, indicating when data are ready. This leads to a "five wire" protocol instead of the usual four. Such a "ready" or "enable" signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have "dummy bytes" inserted, to accommodate the worst case for the slave response time. (Many SPI masters don't support that signal directly, and instead rely on fixed delays.)

一些器件需要一个附加的从从机到主机的流量控制信号来指出什么时候数据就绪。这使得总线变成5线而不是4线。这种“就绪”或者“使能”信号通常是低电平有效的，并且需要在一个命令后或者字之间的关键时间点上使能。如果没有这种信号，数据传输率可能会明显的降低，或者在协议上需要插入“伪字节”来调节到从机响应时间的最坏情况。(很多SPI主机不直接的支持这个信号，它们将依赖一个固定的延时。)

Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the JTAG or SGPIO protocols, or any other protocol that requires messages that are not multiples of 8 bits.

很多SPI芯片只支持8比特的整数倍的消息。这种芯片没法和JTAG、SGPIO协议或者其它需要支持非8比特的整数倍的消息的协议进行交互。

There are even hardware-level differences. Some chips combine MOSI and MISO into a single data line (SI/SO); this is sometimes called "3-Wire" signaling (in contrast to normal "4-wire" SPI). Another SPI flavor removes the chip select line, managing protocol state machine entry/exit using other methods; this isn't usually called 3-Wire though. Anyone needing an external connector for SPI defines their own. Signal levels depend entirely on the chips involved.

甚至还有硬件级的不同。一些芯片把MOSI和MISO合成了一根数据线(SI/SO);这种接口叫做3线信号接口(与普通的4线SPI相比)。另一种SPI省略了片选线，用其他的方式来管理协议状态机的入口和退出; 但是这种方式通常并不叫做3线串口。任何需要用SPI外围接口的人都自己做了定义。信号电平也全部依赖与其所在的芯片。