VHDL_ADC之cic_diffcell

 

 1 library IEEE;
 2 use ieee.std_logic_1164.all;
 3 use ieee.numeric_std.all;
 4 
 5 library edclib;
 6 use edclib.pkg_xxxlib.all;　　-- package from company  7 
 8 --! pipelined comb-chain for cic_filter
 9 entity cic_diffcell is
10 generic
11 (
12     Width        : natural := 20;        --! width        
13     M           : natural := 1            --! difference fifo depth
14 ); 
15 port
16 (
17     RST         : in  std_logic;                            --! Async Reset
18     C        : in  std_logic;                            --! Clock
19     R         : in  std_logic;                            --! needed to clear  registers during sw-reset
20     CEI         : in  std_logic;                            --! new data on input
21     DIN        : in  std_logic_vector(Width-1 downto 0);    --! data in       
22     CEO         : out std_logic;                            --! new data on output
23     DOUT    : out std_logic_vector(Width-1 downto 0)    --! data out 
24 );
25 end cic_diffcell;
26 
27 --! pipelined comb-chain for cic_filter
28 architecture asic of cic_diffcell is
29 type data_type is array (natural range <>) of std_logic_vector( Width-1 downto 0);    --! set of registers 
30 signal reg    : data_type(M downto 0);                        --! delay register (index 0 means DIN)
31 signal diff    : std_logic_vector( Width-1 downto 0);            --! subtraction
32 
33 begin
34 
35 reg(0) <= din when r='0' else (Width-2 => '1', others => '0');
36 
37 --! stage delay
38 gdel: for i in 1 to M generate
39     UDEL : REGDCE generic map(Width) port map(RST,C,CEI,reg(i-1),reg(i));
40 end generate;
41      
42 --subtract
43 diff <= std_logic_vector( signed(din) - signed(reg(m)) ) when r='0' else (others => '0'); 
44 
45 --Output-Reg (Sysclk delay)
46 UOREG: REGDCE generic map(Width) port map(RST,C,CEI, diff, DOUT);
47 
48 --CE-chain
49 UCE: FFD port map(RST,C,CEI,CEO); 
50 
51 end asic;