xilinx spartan-3a oddr

 1 ----------------------------------------------------------------------------------
 2 -- Company: 
 3 -- Engineer: 
 4 -- 
 5 -- Create Date:    16:05:33 05/21/2012 
 6 -- Design Name: 
 7 -- Module Name:    oddr2_top - Behavioral 
 8 -- Project Name: 
 9 -- Target Devices: 
10 -- Tool versions: 
11 -- Description: 
12 --
13 -- Dependencies: 
14 --
15 -- Revision: 
16 -- Revision 0.01 - File Created
17 -- Additional Comments: 
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.all;
22 
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 --use IEEE.NUMERIC_STD.ALL;
26 
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 library UNISIM;
30 use UNISIM.VComponents.all;
31 
32 entity oddr2_top is
33   port (
34     d0  : in  STD_LOGIC;
35     d1  : in  STD_LOGIC;
36     clk : in  STD_LOGIC;
37     q   : out  STD_LOGIC;
38     r   : in  STD_LOGIC;
39     s   : in  STD_LOGIC;
40     ce  : in  STD_LOGIC);
41 end oddr2_top;
42 
43 architecture Behavioral of oddr2_top is
44 
45 begin
46 
47   ODDR2_inst : ODDR2
48   generic map (
49    DDR_ALIGNMENT => "NONE",
50    INIT => '1',
51    SRTYPE => "SYNC")
52   port map (
53    Q => Q, 
54    C0 => CLK,
55    C1 => not(CLK),
56    CE => CE, 
57    D0 => D0, 
58    D1 => D1, 
59    R => R, 
60    S => S
61   );
62 
63   -- End of ODDR2_inst instantiation
64 
65 end Behavioral;