八位串行乘法器的Verilog测试文件和DO文件

串行乘法器的Verilog文档在 http://blog.csdn.net/fantasy_wxe/article/details/6787055 点击打开链接 中介绍的很明确，不在赘述。

测试文档

module multi_CX_tb; // Inputs
reg clk; 
reg [7:0] x; 
reg [7:0] y; 
//reg [1:0] state; // Outputs 
wire [15:0] result; 
//wire [3:0] count; //wire [15:0] pl; //wire [15:0] t; 
//wire [7:0] y_reg; 
// Instantiate the Unit Under Test (UUT) 
multi_CX uut ( .clk(clk), .x(x), .y(y), .result(result) 
//.state(state) //.count(count), //.pl(pl), //.t(t), //.y_reg(y_reg) 
); 
always #5 clk=!clk;
always #8 x=x+1; 
always #8 y=y+1; 
initial begin // Initialize Inputs 
clk = 0; x = 0; y = 0000_0001; 
// state=0; // Wait 100 ns for global reset to finish
 #1000; // Add stimulus here
 end
endmodule

DO文档

#compile the files("vlog":for verilog; "vcom":for VHDL)
vlog multi_CX.V  multi_CX_tb.v


# Load simulation 
vsim -novopt work.multi_CX_tb
# vsim -novopt work.test_drink_machine
# -novopt: don't select "Enable optimmization".


#####################
#add wave
add wave *


# -color: set the wave's color
# -format: set the wave's format, it has three option:
#          "Logic", "Literal" and "Event", if you have not
#          set it, the format is "Logic".
# -radix: set the signal's radix notation.


############################
# Run simulation
run -all