Verilog语言实现4位移位乘法器

modulemulti_4(mplr,mcnd,clk,reset,done,acc,count,mul_state,next_state);

      output  done;

      output [7:0] acc;

      output   [2:0] count;

      output [1:0] mul_state,next_state;

      input [3:0] mplr,mcnd;

      input clk,reset;

      reg [7:0] acc;

      reg [1:0] cs,ns;reg[3:0] mcnd_temp;

      reg[2:0] count;

      reg done;

//定义状态编码为格雷码

parameter[1:0]init=2'b00,add=2'b01,shift=2'b11,compl=2'b10;

assign mul_state=cs;//方便查看状态机状态转换过程

assign next_state=ns;

always @(negedge clk,posedge reset)

       if(reset)

           cs<=init;

       else

           cs<=ns;

//次态计算

always@(cs)

begin

case(cs)

     init:ns=add;

     add:ns=shift;  //当count由0~3变化刚好移动4次，完成4为乘法运算

     shift:if(count==4'b0011)//*****

                  ns=compl;

            else

                  ns=add;

      compl:ns=init;

   endcase

end

//产生输出信号

always@(negedge clk)

  case(cs)

     init:begin

           acc[7:4]<=4'b0000;

           acc[3:0]<=mplr;

           done<=1'b0;

           mcnd_temp[3:0]<=mcnd;

           count<=2'b00;

           end

//判断乘数最高位是否为1，

//则将被乘数加到部分积中

add:if(acc[0]==1'b1)

acc<=acc+{mcnd_temp,4'b0000};

      else acc<=acc;

shift:begin

        count<=count+1'b1;

        acc<={1'b0,acc[7:1]};

        end

compl:done<=1'b1;

endcase

endmodule