sysgen 对带parameter的verilog封装blackbox的问题

例如这样一个小模块

module mul#(
parameter MUL_A_WIDTH = 10,
parameter MUL_B_WIDTH = 10,
parameter MUL_C_WIDTH =  MUL_A_WIDTH+MUL_B_WIDTH-1
)

(
input [MUL_A_WIDTH-1:0] a,
input [MUL_B_WIDTH-1:0] b,
output [MUL_C_WIDTH-1:0] c
);

assign c = a*b;

endmodule

 

封装进blackbox后，对其.m进行修改

function mul_config(this_block)

  % Revision History:
  %
  %   29-Jan-2019  (09:34 hours):
  %     Original code was machine generated by Xilinx's System Generator after parsing
  %     E:\BLE\mul.v
  %
  %

  this_block.setTopLevelLanguage('Verilog');

  this_block.setEntityName('mul');

  % System Generator has to assume that your entity  has a combinational feed through; 
  %   if it  doesn't, then comment out the following line:
  this_block.tagAsCombinational;

  this_block.addSimulinkInport('a');
  this_block.addSimulinkInport('b');

  this_block.addSimulinkOutport('c');
  
  this_block.addGeneric('MUL_A_WIDTH',this_block.port('a').width);
  this_block.addGeneric('MUL_B_WIDTH',this_block.port('b').width);

  % -----------------------------
  if (this_block.inputTypesKnown)
      % do input type checking, dynamic output type and generic setup in this code block.
      %% add by wc
      this_block.port('a').useHDLVector(true);
      this_block.port('b').useHDLVector(true);

      c_port = this_block.port('c');
      output_bitwidth = this_block.port('a').width+this_block.port('b').width-1;
      c_port.width = output_bitwidth;
      c_port.makeSigned;
      c_port.binpt = 0;

  
  
  end  % if(inputTypesKnown)
  % -----------------------------

  % System Generator found no apparent clock signals in the HDL, assuming combinational logic.
  % -----------------------------
   if (this_block.inputRatesKnown)
     inputRates = this_block.inputRates; 
     uniqueInputRates = unique(inputRates); 
     outputRate = uniqueInputRates(1);
     for i = 2:length(uniqueInputRates)
       if (uniqueInputRates(i) ~= Inf)
         outputRate = gcd(outputRate,uniqueInputRates(i));
       end
     end  % for(i)
     for i = 1:this_block.numSimulinkOutports 
       this_block.outport(i).setRate(outputRate); 
     end  % for(i)
   end  % if(inputRatesKnown)
  % -----------------------------

    uniqueInputRates = unique(this_block.getInputRates);

  % (!) Custimize the following generic settings as appropriate. If any settings depend
  %      on input types, make the settings in the "inputTypesKnown" code block.
  %      The addGeneric function takes  3 parameters, generic name, type and constant value.
  %      Supported types are boolean, real, integer and string.
  %% add by wc
  %this_block.addGeneric('MUL_A_WIDTH','integer','10');
  %this_block.addGeneric('MUL_B_WIDTH','integer','10');

  %this_block.addGeneric('MUL_C_WIDTH','','');

  % Add addtional source files as needed.
  %  |-------------
  %  | Add files in the order in which they should be compiled.
  %  | If two files "a.vhd" and "b.vhd" contain the entities
  %  | entity_a and entity_b, and entity_a contains a
  %  | component of type entity_b, the correct sequence of
  %  | addFile() calls would be:
  %  |    this_block.addFile('b.vhd');
  %  |    this_block.addFile('a.vhd');
  %  |-------------

  %    this_block.addFile('');
  %    this_block.addFile('');
  this_block.addFile('mul.v');

return;

但仿真都是NaN。不知道是不是不支持