To reduce FPGA compilation time by using partition tool of Quartus

Author : monokent

First written in 2015.

A simple way to reduce Quartus compilation time effectively. You can use it to :

1. reduce compilation time significantly (my project from 42 min to 25 min, 40% reduction).
2. lock the modules unchanged, preserve the timing performance.

The more partitions being locked, the better time saving would likely be.

Steps of operation:

1. First compile the whole project and make sure the result is correct.
2. Open Design Partitions Window of Quartus (Menu --> Assignments).
3. Divide project into several partitions such as different functional units.
4. Set those unchanged partitions Netlist Type as Post-fit and they will maintain the placement and routing result of last compilation. As a result the time of new compilation will be reduced.
5. If you want to modify one Post-fit partition, just change the Netlist Type to Source File, then it will be recompiled the next time.

There are some tips about division plan of partitions and interface design, we will talk about it later :)