Vivado 约束条件出错
When generating a bitstream, the following error messages occur:
ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 3 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. Problem ports: clk, din, dout.
ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 3 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. Problem ports: clk, din, dout.
解决方案
The error message is to notify customers that they need to set IOSTANDARD and PACKAGE_PIN, in order to protect devices from accidental damage that could be caused by the tools randomly choosing a pin location or IOSTANDARD without knowledge of the board voltage or connections.
For example:
- If a pin is tied to ground on a board and Vivado chooses this pin as an output that is driving high, this causes contention.
- If you have a termination scheme on the board for a pin that is the HSTL or SSTL recommended termination, and Vivado chooses LVCMOS18 (default), the signal integrity of the signal will be less than optimal.
The default I/O standard for the 7 Series is LVCMOS18 for single-ended signals for all banks. The default I/O standard was LVCMOS25 in previous architectures.
Below are possible solutions to these errors.
1. (Recommended) Add IOSTANDARD and PACKAGE_PIN constraints for all I/Os in the design.
2. If you do not care about those unconstrained I/Os, you use one of below solutions.
- For a GUI project flow, create a .tcl file and put below two commands in it. Specify this .tcl file in the "tcl.pre" option in "Bitstream Settings". Then you can re-run "Generate Bitstream" without re-running Implementation.
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]