FPGA按键防抖动程序_Verilog

 

module fangdoudong( clk,reset,key_in_1,key_in_2,key_in_3,led_1,led_2,led_3 );
input clk ;  //50MHz
input reset;  //高电平有效
input  key_in_1,key_in_2,key_in_3;   //开关key_in_1 对应led_1，以此类推
output reg led_1,led_2,led_3 ;     //高电平时，led亮
reg [2:0] flag,key_1,key_2 ;  //flag代表标志位，key_1代表当前按键的状态，key_2存储key_1的状态
reg [19:0] count ;      //计数功能,延时20ms

always @(posedge clk)   //reset低电平时，复位
  begin
    if ( reset == 0 )
       begin
         flag <= 3'b000;
         count <= 3'b000;
         led_1 <= 0;
         led_2 <= 0;
         led_3 <= 0;
         key_1 <= 0;
         key_2 <= 0;
       end
  end
always @(posedge clk)   //key_1代表当前按键的状态
  begin
    if ( reset == 1 )
       key_1 <= {key_in_1,key_in_2,key_in_3} ;
  end
always @(posedge clk)   //key_2存储key_1的状态
  begin
    if ( reset == 1 )
       key_2 <= key_1 ;
  end
always @(posedge clk)
  begin
    if ( reset == 1 )
       begin
           flag <= key_1 ^ key_2;  //key_2与key_1的值不同，说明按键按下或是处于开关抖动状态，立即开始计时
        if ( flag  )
         begin
           count <= count + 1 ;
            if ( count == 20'hfffff )   //计时满，立即用开关的稳定状态驱动LED
             led_1 <= key_in_1 ;
             led_2 <= key_in_2;
             led_3 <= key_in_3;
         end
        if ( flag == 0 && count != 0 )    //在判断key_2与key_1的值是否相同时。若处在抖动期很可能相同，使flag=0，
                                               但是也要继续计数，以满足延时20ms的目的
         begin
           count <= count + 1 ;
            if ( count == 20'hfffff )
             led_1 <= key_in_1 ;
             led_2 <= key_in_2;
             led_3 <= key_in_3;
         end
       end
  end          

endmodule