HAL库系统时钟配置的相关结构体
结构体1：
RCC_OscInitTypeDef
在stm32l0xx_hal_rcc.h中
RCC内部/外部振荡器(HSE, HSI, LSE, LSI)配置结构体定义
typedef struct
{
uint32_t OscillatorType; //①，选定将被配置的振荡器
uint32_t HSEState; //②，HSE状态
uint32_t LSEState; //③，LSE状态
uint32_t HSIState; //④，HSI状态
uint32_t HSICalibrationValue; //⑤，HSI校准调整值
uint32_t LSIState; //⑥，LSI状态
#if defined(RCC_HSI48_SUPPORT)
uint32_t HSI48State; //⑦，HSI状态，#if defined(RCC_HSI48_SUPPORT)
#endif
uint32_t MSIState; //⑧，MSI状态
uint32_t MSICalibrationValue; //⑨，MSI校准调整值
uint32_t MSIClockRange; //⑩，MSI频率范围
RCC_PLLInitTypeDef PLL; //⑾，PLL结构体参数
} RCC_OscInitTypeDef;
①参数可为：
RCC_OSCILLATORTYPE_NONE
RCC_OSCILLATORTYPE_HSE
RCC_OSCILLATORTYPE_HSI
RCC_OSCILLATORTYPE_LSE
RCC_OSCILLATORTYPE_LSI
RCC_OSCILLATORTYPE_MSI
RCC_OSCILLATORTYPE_HSI48 //if defined(RCC_HSI48_SUPPORT)
②参数可为：
RCC_HSE_OFF //HSE clock deactivation
RCC_HSE_ON //HSE clock activation
RCC_HSE_BYPASS //External clock source for HSE clock
③参数可为：
RCC_LSE_OFF //LSE clock deactivation
RCC_LSE_ON //LSE clock activation
RCC_LSE_BYPASS //External clock source for LSE clock
④参数可为：
RCC_HSI_OFF //HSI clock deactivation
RCC_HSI_ON //HSI clock activation
RCC_HSI_DIV4 //HSI_DIV4 clock activation
RCC_HSI_OUTEN //HSI_OUTEN clock activation //if defined(RCC_CR_HSIOUTEN)
RCC_HSICALIBRATION_DEFAULT //Default HSI calibration trimming value
⑤参数可为：
[0x00, 0x1f]，默认为RCC_HSICALIBRATION_DEFAULT，宏定义为0x00U
⑥参数可为：
RCC_LSI_OFF //LSI clock deactivation
RCC_LSI_ON //LSI clock activation
⑦参数可为：
RCC_HSI48_OFF
RCC_HSI48_ON
⑧参数可为：
RCC_MSI_OFF
RCC_MSI_ON
RCC_MSICALIBRATION_DEFAULT //Default MSI calibration trimming value
⑨参数可为：
[0x00, 0xff]，默认为RCC_MSICALIBRATION_DEFAULT，为((uint32_t)0x00000000U)
⑩参数可为：
RCC_MSIRANGE_0 //MSI = 65.536 KHz
RCC_MSIRANGE_1 //MSI = 131.072 KHz
RCC_MSIRANGE_2 //MSI = 262.144 KHz
RCC_MSIRANGE_3 //MSI = 524.288 KHz
RCC_MSIRANGE_4 //MSI = 1.048 MHz
RCC_MSIRANGE_5 //MSI = 2.097 MHz
RCC_MSIRANGE_6 //MSI = 4.194 MHz
***************************************************************************************
结构体2：
RCC_ClkInitTypeDef
在stm32l0xx_hal_rcc.h中
在RCC系统，AHB和APB总线时钟配置结构体定义
typedef struct
{
uint32_t ClockType; //①，选定将被配置的时钟
uint32_t SYSCLKSource; //②，用作系统时钟的时钟源选择
uint32_t AHBCLKDivider; //③，AHB时钟(HCLK)分频器，该时钟由SYSCLK而来
uint32_t APB1CLKDivider; //④，APB1时钟(PCLK1)分频器，该时钟由HCLK而来
uint32_t APB2CLKDivider; //⑤，APB2时钟(PCLK2)分频器，该时钟由HCLK而来
} RCC_ClkInitTypeDef;
①参数可为：
RCC_CLOCKTYPE_SYSCLK //SYSCLK to configure
RCC_CLOCKTYPE_HCLK //HCLK to configure
RCC_CLOCKTYPE_PCLK1 //PCLK1 to configure
RCC_CLOCKTYPE_PCLK2 //PCLK2 to configure
②参数可为：
RCC_SYSCLKSOURCE_MSI //MSI selected as system clock
RCC_SYSCLKSOURCE_HSI //HSI selected as system clock
RCC_SYSCLKSOURCE_HSE //HSE selected as system clock
RCC_SYSCLKSOURCE_PLLCLK //PLL selected as system clock
③参数可为：
RCC_SYSCLK_DIV1 //SYSCLK not divided
RCC_SYSCLK_DIV2 //SYSCLK divided by 2
RCC_SYSCLK_DIV4 //SYSCLK divided by 4
RCC_SYSCLK_DIV8 //SYSCLK divided by 8
RCC_SYSCLK_DIV16 //SYSCLK divided by 16
RCC_SYSCLK_DIV64 //SYSCLK divided by 64
RCC_SYSCLK_DIV128 //SYSCLK divided by 128
RCC_SYSCLK_DIV256 //SYSCLK divided by 256
RCC_SYSCLK_DIV512 //SYSCLK divided by 512
④⑤参数可为：
RCC_HCLK_DIV1 //HCLK not divided
RCC_HCLK_DIV2 //HCLK divided by 2
RCC_HCLK_DIV4 //HCLK divided by 4
RCC_HCLK_DIV8 //HCLK divided by 8
RCC_HCLK_DIV16 //HCLK divided by 16
***************************************************************************************
结构体3：
RCC_PLLInitTypeDef
在stm32l0xx_hal_rcc.h中
RCC PLL配置结构体定义
typedef struct
{
uint32_t PLLState; //①，PLL状态
uint32_t PLLSource; //②，PLL输入时钟源
uint32_t PLLMUL; //③，PLL输入时钟倍增系数
uint32_t PLLDIV; //④，PLL输入时钟分频系数
} RCC_PLLInitTypeDef;
①参数可为：
RCC_PLL_NONE //PLL is not configured
RCC_PLL_OFF //PLL deactivation
RCC_PLL_ON //PLL activation
②参数可为：
RCC_PLLSOURCE_HSI //HSI clock selected as PLL entry clock sourc
RCC_PLLSOURCE_HSE //HSE clock selected as PLL entry clock source
③参数可为：
RCC_PLL_MUL3
RCC_PLL_MUL4
RCC_PLL_MUL6
RCC_PLL_MUL8
RCC_PLL_MUL12
RCC_PLL_MUL16
RCC_PLL_MUL24
RCC_PLL_MUL32
RCC_PLL_MUL48
④参数可为：
RCC_PLL_DIV2
RCC_PLL_DIV3
RCC_PLL_DIV4