jacky_shen

8086 instructions

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Complete 8086 instruction set

Quick reference:

AAA
AAD
AAM
AAS
ADC
ADD
AND
CALL
CBW
CLC
CLD
CLI
CMC
CMP

CMPSB
CMPSW
CWD
DAA
DAS
DEC
DIV
HLT
IDIV
IMUL
IN
INC
INT
INTO
IRET
JA

JAE
JB
JBE
JC
JCXZ
JE
JG
JGE
JL
JLE
JMP
JNA
JNAE
JNB

JNBE
JNC
JNE
JNG
JNGE
JNL
JNLE
JNO
JNP
JNS
JNZ
JO
JP
JPE

JPO
JS
JZ
LAHF
LDS
LEA
LES
LODSB
LODSW
LOOP
LOOPE
LOOPNE
LOOPNZ
LOOPZ

MOV
MOVSB
MOVSW
MUL
NEG
NOP
NOT
OR
OUT
POP
POPA
POPF
PUSH
PUSHA
PUSHF
RCL

RCR
REP
REPE
REPNE
REPNZ
REPZ
RET
RETF
ROL
ROR
SAHF
SAL
SAR
SBB

SCASB
SCASW
SHL
SHR
STC
STD
STI
STOSB
STOSW
SUB
TEST
XCHG
XLATB
XOR

Operand types:
操作数类型:

REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.

SREG: DS, ES, SS, and only as second operand: CS.

memory: [BX], [BX+SI+7], variable, etc...(see Memory Access).

immediate: 5, -24, 3Fh, 10001101b, etc...

Notes:
备注:

When two operands are required for an instruction they are separated by comma. For example:
一个指令中有两个操作数的时候用逗号(,)分隔. 如下:

REG, memory
When there are two operands, both operands must have the same size (except shift and rotate instructions). For example:
指令中有两个操作数的时候，他们的大小必须相等 (除非使用类型转换).如下:

AL, DL
DX, AX
m1 DB ?
AL, m1
m2 DW ?
AX, m2
Some instructions allow several operand combinations. For example:
有些指令允许将几个操作数合并.如下:

memory, immediate
REG, immediate

memory, REG
REG, SREG
Some examples contain macros, so it is advisable to use Shift + F8 hot key to Step Over (to make macro code execute at maximum speed set step delay to zero), otherwise emulator will step through each instruction of a macro. Here is an example that uses PRINTN macro:
```
 
```

These marks are used to show the state of the flags:
如下是一些状态标志:

1 - instruction sets this flag to 1.
指令设置标志为1
0 - instruction sets this flag to 0.
指令设置标志为0
r - flag value depends on result of the instruction.
标志的值依赖于指令的返回指
? - flag value is undefined (maybe 1 or 0).
标志的值不确定(1或0都可能)

Some instructions generate exactly the same machine code, so disassembler may have a problem decoding to your original code. This is especially important for Conditional Jump instructions (see "Program Flow Control" in Tutorials for more information).

Instructions in alphabetical order:

Instruction
指令

Operands
操作数

Description
描述

AAA

No operands

ASCII Adjust after Addition.
Corrects result in AH and AL after addition when working with BCD values.

It works according to the following Algorithm:

if low nibble of AL > 9 or AF = 1 then:

AL = AL + 6
AH = AH + 1
AF = 1
CF = 1

else

AF = 0
CF = 0

in both cases:
clear the high nibble of AL.

Example:

C	Z	S	O	P	A
r	?	?	?	?	r

AAD

No operands

ASCII Adjust before Division.
Prepares two BCD values for division.

Algorithm:

AL = (AH * 10) + AL
AH = 0

Example:

C	Z	S	O	P	A
?	r	r	?	r	?

AAM

No operands

ASCII Adjust after Multiplication.
Corrects the result of multiplication of two BCD values.

Algorithm:

AH = AL / 10
AL = remainder

Example:

C	Z	S	O	P	A
?	r	r	?	r	?

AAS

No operands

ASCII Adjust after Subtraction.
Corrects result in AH and AL after subtraction when working with BCD values.

Algorithm:

if low nibble of AL > 9 or AF = 1 then:

AL = AL - 6
AH = AH - 1
AF = 1
CF = 1

else

AF = 0
CF = 0

in both cases:
clear the high nibble of AL.

Example:

C	Z	S	O	P	A
r	?	?	?	?	r

ADC

REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate

Add with Carry.

Algorithm:

operand1 = operand1 + operand2 + CF

Example:

C	Z	S	O	P	A
r	r	r	r	r	r

ADD

REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate

Add.

Algorithm:

operand1 = operand1 + operand2

Example:

C	Z	S	O	P	A
r	r	r	r	r	r

AND

REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate

Logical AND between all bits of two operands. Result is stored in operand1.

These rules apply:

1 AND 1 = 1
1 AND 0 = 0
0 AND 1 = 0
0 AND 0 = 0

Example:

C	Z	S	O	P
0	r	r	0	r

CALL

procedure name
label
4-byte address

Transfers control to procedure, return address is (IP) is pushed to stack. 4-byte address may be entered in this form: 1234h:5678h, first value is a segment second value is an offset (this is a far call, so CS is also pushed to stack).

Example:

C	Z	S	O	P	A
unchanged

CBW

No operands

Convert byte into word.

Algorithm:

if high bit of AL = 1 then:

AH = 255 (0FFh)

else

AH = 0

Example:

C	Z	S	O	P	A
unchanged

CLC

No operands

Clear Carry flag.

Algorithm:

CF = 0

CLD

No operands

Clear Direction flag. SI and DI will be incremented by chain instructions: CMPSB, CMPSW, LODSB, LODSW, MOVSB, MOVSW, STOSB, STOSW.

Algorithm:

DF = 0

CLI

No operands

Clear Interrupt enable flag. This disables hardware interrupts.

Algorithm:

IF = 0

CMC

No operands

Complement Carry flag. Inverts value of CF.

Algorithm:

if CF = 1 then CF = 0
if CF = 0 then CF = 1

CMP

REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate

Compare.

Algorithm:

operand1 - operand2

result is not stored anywhere, flags are set (OF, SF, ZF, AF, PF, CF) according to result.

Example:

C	Z	S	O	P	A
r	r	r	r	r	r

CMPSB

No operands

Compare bytes: ES:[DI] from DS:[SI].

Algorithm:

DS:[SI] - ES:[DI]
set flags according to result:
OF, SF, ZF, AF, PF, CF
if DF = 0 then
- SI = SI + 1
- DI = DI + 1
else
- SI = SI - 1
- DI = DI - 1

Example:
see cmpsb.asm in Samples.

C	Z	S	O	P	A
r	r	r	r	r	r

CMPSW

No operands

Compare words: ES:[DI] from DS:[SI].

Algorithm:

DS:[SI] - ES:[DI]
set flags according to result:
OF, SF, ZF, AF, PF, CF
if DF = 0 then
- SI = SI + 2
- DI = DI + 2
else
- SI = SI - 2
- DI = DI - 2

Example:
see cmpsw.asm in Samples.

C	Z	S	O	P	A
r	r	r	r	r	r

CWD

No operands

Convert Word to Double word.

Algorithm:

if high bit of AX = 1 then:

DX = 65535 (0FFFFh)

else

DX = 0

Example:

C	Z	S	O	P	A
unchanged

DAA

No operands

Decimal adjust After Addition.
Corrects the result of addition of two packed BCD values.

Algorithm:

if low nibble of AL > 9 or AF = 1 then:

AL = AL + 6
AF = 1

if AL > 9Fh or CF = 1 then:

AL = AL + 60h
CF = 1

Example:

C	Z	S	O	P	A
r	r	r	r	r	r

DAS

No operands

Decimal adjust After Subtraction.
Corrects the result of subtraction of two packed BCD values.

Algorithm:

if low nibble of AL > 9 or AF = 1 then:

AL = AL - 6
AF = 1

if AL > 9Fh or CF = 1 then:

AL = AL - 60h
CF = 1

Example:

C	Z	S	O	P	A
r	r	r	r	r	r

DEC

REG
memory

Decrement.

Algorithm:

operand = operand - 1

Example:

Z	S	O	P	A
r	r	r	r	r

CF - unchanged!

DIV

REG
memory

Unsigned divide.

Algorithm:

when operand is a byte:
AL = AX / operand
AH = remainder (modulus)

when operand is a word:
AX = (DX AX) / operand
DX = remainder (modulus)

Example:

C	Z	S	O	P	A
?	?	?	?	?	?

HLT

No operands

Halt the System.

Example:

C	Z	S	O	P	A
unchanged

IDIV

REG
memory

Signed divide.

Algorithm:

when operand is a byte:
AL = AX / operand
AH = remainder (modulus)

when operand is a word:
AX = (DX AX) / operand
DX = remainder (modulus)

Example:

C	Z	S	O	P	A
?	?	?	?	?	?

IMUL

REG
memory

Signed multiply.

Algorithm:

when operand is a byte:
AX = AL * operand.

when operand is a word:
(DX AX) = AX * operand.

Example:

C	Z	S	O	P	A
r	?	?	r	?	?

CF=OF=0 when result fits into operand of IMUL.

AL, im.byte
AL, DX
AX, im.byte
AX, DX

Input from port into AL or AX.
Second operand is a port number. If required to access port number over 255 - DX register should be used.
Example:

C	Z	S	O	P	A
unchanged

INC

REG
memory

Increment.

Algorithm:

operand = operand + 1

Example:

Z	S	O	P	A
r	r	r	r	r

CF - unchanged!

INT

immediate byte

Interrupt numbered by immediate byte (0..255).

Algorithm:

Push to stack:
- flags register
- CS
- IP
IF = 0
Transfer control to interrupt procedure

Example:

C	Z	S	O	P	A	I
unchanged						0

INTO

No operands

Interrupt 4 if Overflow flag is 1.

Algorithm:

if OF = 1 then INT 4

Example:

IRET

No operands

Interrupt Return.

Algorithm:

Pop from stack:
- IP
- CS
- flags register

C	Z	S	O	P	A
popped

label

Short Jump if first operand is Above second operand (as set by CMP instruction). Unsigned.

Algorithm:

if (CF = 0) and (ZF = 0) then jump

Example:

C	Z	S	O	P	A
unchanged

JAE

label

Short Jump if first operand is Above or Equal to second operand (as set by CMP instruction). Unsigned.

Algorithm:

if CF = 0 then jump

Example:

C	Z	S	O	P	A
unchanged

label

Short Jump if first operand is Below second operand (as set by CMP instruction). Unsigned.

Algorithm:

if CF = 1 then jump

Example:

C	Z	S	O	P	A
unchanged

JBE

label

Short Jump if first operand is Below or Equal to second operand (as set by CMP instruction). Unsigned.

Algorithm:

if CF = 1 or ZF = 1 then jump

Example:

C	Z	S	O	P	A
unchanged

label

Short Jump if Carry flag is set to 1.

Algorithm:

if CF = 1 then jump

Example:

C	Z	S	O	P	A
unchanged

JCXZ

label

Short Jump if CX register is 0.

Algorithm:

if CX = 0 then jump

Example:

C	Z	S	O	P	A
unchanged

label

Short Jump if first operand is Equal to second operand (as set by CMP instruction). Signed/Unsigned.

Algorithm:

if ZF = 1 then jump

Example:

C	Z	S	O	P	A
unchanged

label

Short Jump if first operand is Greater then second operand (as set by CMP instruction). Signed.

Algorithm:

if (ZF = 0) and (SF = OF) then jump

Example:

C	Z	S	O	P	A
unchanged

JGE

label

Short Jump if first operand is Greater or Equal to second operand (as set by CMP instruction). Signed.

Algorithm:

if SF = OF then jump

Example:

C	Z	S	O	P	A
unchanged

label

Short Jump if first operand is Less then second operand (as set by CMP instruction). Signed.

Algorithm:

if SF <> OF then jump

Example:

C	Z	S	O	P	A
unchanged

JLE

label

Short Jump if first operand is Less or Equal to second operand (as set by CMP instruction). Signed.

Algorithm:

if SF <> OF or ZF = 1 then jump

Example:

C	Z	S	O	P	A
unchanged

JMP

label
4-byte address

Unconditional Jump. Transfers control to another part of the program. 4-byte address may be entered in this form: 1234h:5678h, first value is a segment second value is an offset.

Algorithm:

always jump

Example:

C	Z	S	O	P	A
unchanged

JNA

label

Short Jump if first operand is Not Above second operand (as set by CMP instruction). Unsigned.

Algorithm:

if CF = 1 or ZF = 1 then jump

Example:

C	Z	S	O	P	A
unchanged

JNAE

label

Short Jump if first operand is Not Above and Not Equal to second operand (as set by CMP instruction). Unsigned.

Algorithm:

if CF = 1 then jump

Example:

C	Z	S	O	P	A
unchanged

JNB

label

Short Jump if first operand is Not Below second operand (as set by CMP instruction). Unsigned.

Algorithm:

if CF = 0 then jump

Example:

C	Z	S	O	P	A
unchanged

JNBE

label

Short Jump if first operand is Not Below and Not Equal to second operand (as set by CMP instruction). Unsigned.

Algorithm:

if (CF = 0) and (ZF = 0) then jump

Example:

C	Z	S	O	P	A
unchanged

JNC

label

Short Jump if Carry flag is set to 0.

Algorithm:

if CF = 0 then jump

Example:

C	Z	S	O	P	A
unchanged

JNE

label

Short Jump if first operand is Not Equal to second operand (as set by CMP instruction). Signed/Unsigned.

Algorithm:

if ZF = 0 then jump

Example:

C	Z	S	O	P	A
unchanged

JNG

label

Short Jump if first operand is Not Greater then second operand (as set by CMP instruction). Signed.

Algorithm:

if (ZF = 1) and (SF <> OF) then jump

Example:

C	Z	S	O	P	A
unchanged

JNGE

label

Short Jump if first operand is Not Greater and Not Equal to second operand (as set by CMP instruction). Signed.

Algorithm:

if SF <> OF then jump

Example:

C	Z	S	O	P	A
unchanged

JNL

label

Short Jump if first operand is Not Less then second operand (as set by CMP instruction). Signed.

Algorithm:

if SF = OF then jump

Example:

C	Z	S	O	P	A
unchanged

JNLE

label

Short Jump if first operand is Not Less and Not Equal to second operand (as set by CMP instruction). Signed.

Algorithm:

if (SF = OF) and (ZF = 0) then jump

Example:

C	Z	S	O	P	A
unchanged

JNO

label

Short Jump if Not Overflow.

Algorithm:

if OF = 0 then jump

Example:

C	Z	S	O	P	A
unchanged

JNP

label

Short Jump if No Parity (odd). Only 8 low bits of result are checked. Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.

Algorithm:

if PF = 0 then jump

Example:

C	Z	S	O	P	A
unchanged

JNS

label

Short Jump if Not Signed (if positive). Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.

Algorithm:

if SF = 0 then jump

Example:

C	Z	S	O	P	A
unchanged

JNZ

label

Short Jump if Not Zero (not equal). Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.

Algorithm:

if ZF = 0 then jump

Example:

C	Z	S	O	P	A
unchanged

label

Short Jump if Overflow.

Algorithm:

if OF = 1 then jump

Example:

C	Z	S	O	P	A
unchanged

label

Short Jump if Parity (even). Only 8 low bits of result are checked. Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.

Algorithm:

if PF = 1 then jump

Example:

C	Z	S	O	P	A
unchanged

JPE

label

Short Jump if Parity Even. Only 8 low bits of result are checked. Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.

Algorithm:

if PF = 1 then jump

Example:

C	Z	S	O	P	A
unchanged

JPO

label

Short Jump if Parity Odd. Only 8 low bits of result are checked. Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.

Algorithm:

if PF = 0 then jump

Example:

C	Z	S	O	P	A
unchanged

label

Short Jump if Signed (if negative). Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.

Algorithm:

if SF = 1 then jump

Example:

C	Z	S	O	P	A
unchanged

label

Short Jump if Zero (equal). Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.

Algorithm:

if ZF = 1 then jump

Example:

C	Z	S	O	P	A
unchanged

LAHF

No operands

Load AH from 8 low bits of Flags register.

Algorithm:

AH = flags register

bits 1, 3, 5 are reserved.

C	Z	S	O	P	A
unchanged

LDS

REG, memory

Load memory double word into word register and DS.

Algorithm:

REG = first word
DS = second word

Example:

AX is set to 1234h, DS is set to 5678h.

C	Z	S	O	P	A
unchanged

LEA

REG, memory

Load Effective Address.

Algorithm:

REG = address of memory (offset)

Generally this instruction is replaced by MOV when assembling when possible.

Example:

AX is set to: 0104h.
LEA instruction takes 3 bytes, RET takes 1 byte, we start at 100h, so the address of 'm' is 104h.

C	Z	S	O	P	A
unchanged

LES

REG, memory

Load memory double word into word register and ES.

Algorithm:

REG = first word
ES = second word

Example:

AX is set to 1234h, ES is set to 5678h.

C	Z	S	O	P	A
unchanged

LODSB

No operands

Load byte at DS:[SI] into AL. Update SI.

Algorithm:

AL = DS:[SI]
if DF = 0 then
- SI = SI + 1
else
- SI = SI - 1

Example:

C	Z	S	O	P	A
unchanged

LODSW

No operands

Load word at DS:[SI] into AX. Update SI.

Algorithm:

AX = DS:[SI]
if DF = 0 then
- SI = SI + 2
else
- SI = SI - 2

Example:

C	Z	S	O	P	A
unchanged

LOOP

label

Decrease CX, jump to label if CX not zero.

Algorithm:

CX = CX - 1
if CX <> 0 then
- jump
else
- no jump, continue

Example:

C	Z	S	O	P	A
unchanged

LOOPE

label

Decrease CX, jump to label if CX not zero and Equal (ZF = 1).

Algorithm:

CX = CX - 1
if (CX <> 0) and (ZF = 1) then
- jump
else
- no jump, continue

Example:

C	Z	S	O	P	A
unchanged

LOOPNE

label

Decrease CX, jump to label if CX not zero and Not Equal (ZF = 0).

Algorithm:

CX = CX - 1
if (CX <> 0) and (ZF = 0) then
- jump
else
- no jump, continue

Example:

C	Z	S	O	P	A
unchanged

LOOPNZ

label

Decrease CX, jump to label if CX not zero and ZF = 0.

Algorithm:

CX = CX - 1
if (CX <> 0) and (ZF = 0) then
- jump
else
- no jump, continue

Example:

C	Z	S	O	P	A
unchanged

LOOPZ

label

Decrease CX, jump to label if CX not zero and ZF = 1.

Algorithm:

CX = CX - 1
if (CX <> 0) and (ZF = 1) then
- jump
else
- no jump, continue

Example:

C	Z	S	O	P	A
unchanged

MOV

REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate

SREG, memory
memory, SREG
REG, SREG
SREG, REG

Copy operand2 to operand1.

The MOV instruction cannot:

set the value of the CS and IP registers.
copy value of one segment register to another segment register (should copy to general register first).
copy immediate value to segment register (should copy to general register first).

Algorithm:

operand1 = operand2

Example:

C	Z	S	O	P	A
unchanged

MOVSB

No operands

Copy byte at DS:[SI] to ES:[DI]. Update SI and DI.

Algorithm:

ES:[DI] = DS:[SI]
if DF = 0 then
- SI = SI + 1
- DI = DI + 1
else
- SI = SI - 1
- DI = DI - 1

Example:

C	Z	S	O	P	A
unchanged

MOVSW

No operands

Copy word at DS:[SI] to ES:[DI]. Update SI and DI.

Algorithm:

ES:[DI] = DS:[SI]
if DF = 0 then
- SI = SI + 2
- DI = DI + 2
else
- SI = SI - 2
- DI = DI - 2

Example:

C	Z	S	O	P	A
unchanged

MUL

REG
memory

Unsigned multiply.

Algorithm:

when operand is a byte:
AX = AL * operand.

when operand is a word:
(DX AX) = AX * operand.

Example:

C	Z	S	O	P	A
r	?	?	r	?	?

CF=OF=0 when high section of the result is zero.

NEG

REG
memory

Negate. Makes operand negative (two's complement).

Algorithm:

Invert all bits of the operand
Add 1 to inverted operand

Example:

C	Z	S	O	P	A
r	r	r	r	r	r

NOP

No operands

No Operation.

Algorithm:

Do nothing

Example:

C	Z	S	O	P	A
unchanged

NOT

REG
memory

Invert each bit of the operand.

Algorithm:

if bit is 1 turn it to 0.
if bit is 0 turn it to 1.

Example:

C	Z	S	O	P	A
unchanged

REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate

Logical OR between all bits of two operands. Result is stored in first operand.

These rules apply:

1 OR 1 = 1
1 OR 0 = 1
0 OR 1 = 1
0 OR 0 = 0

Example:

C	Z	S	O	P	A
0	r	r	0	r	?

OUT

im.byte, AL
im.byte, AX
DX, AL
DX, AX

Output from AL or AX to port.
First operand is a port number. If required to access port number over 255 - DX register should be used.

Example:

C	Z	S	O	P	A
unchanged

POP

REG
SREG
memory

Get 16 bit value from the stack.

Algorithm:

operand = SS:[SP] (top of the stack)
SP = SP + 2

Example:

C	Z	S	O	P	A
unchanged

POPA

No operands

Pop all general purpose registers DI, SI, BP, SP, BX, DX, CX, AX from the stack.
SP value is ignored, it is Popped but not set to SP register).

Note: this instruction works only on 80186 CPU and later!

Algorithm:

POP DI
POP SI
POP BP
POP xx (SP value ignored)
POP BX
POP DX
POP CX
POP AX

C	Z	S	O	P	A
unchanged

POPF

No operands

Get flags register from the stack.

Algorithm:

flags = SS:[SP] (top of the stack)
SP = SP + 2

C	Z	S	O	P	A
popped

PUSH

REG
SREG
memory
immediate

Store 16 bit value in the stack.

Note: PUSH immediate works only on 80186 CPU and later!

Algorithm:

SP = SP - 2
SS:[SP] (top of the stack) = operand

Example:

C	Z	S	O	P	A
unchanged

PUSHA

No operands

Push all general purpose registers AX, CX, DX, BX, SP, BP, SI, DI in the stack.
Original value of SP register (before PUSHA) is used.

Note: this instruction works only on 80186 CPU and later!

Algorithm:

PUSH AX
PUSH CX
PUSH DX
PUSH BX
PUSH SP
PUSH BP
PUSH SI
PUSH DI

C	Z	S	O	P	A
unchanged

PUSHF

No operands

Store flags register in the stack.

Algorithm:

SP = SP - 2
SS:[SP] (top of the stack) = flags

C	Z	S	O	P	A
unchanged

RCL

memory, immediate
REG, immediate

memory, CL
REG, CL

Rotate operand1 left through Carry Flag. The number of rotates is set by operand2.
When immediate is greater then 1, assembler generates several RCL xx, 1 instructions because 8086 has machine code only for this instruction (the same principle works for all other shift/rotate instructions).

Algorithm:

shift all bits left, the bit that goes off is set to CF and previous value of CF is inserted to the right-most position.

Example:

C	O
r	r

OF=0 if first operand keeps original sign.

RCR

memory, immediate
REG, immediate

memory, CL
REG, CL

Rotate operand1 right through Carry Flag. The number of rotates is set by operand2.

Algorithm:

shift all bits right, the bit that goes off is set to CF and previous value of CF is inserted to the left-most position.

Example:

C	O
r	r

OF=0 if first operand keeps original sign.

REP

chain instruction

Repeat following MOVSB, MOVSW, LODSB, LODSW, STOSB, STOSW instructions CX times.

Algorithm:

check_cx:

if CX <> 0 then

do following chain instruction
CX = CX - 1
go back to check_cx

else

exit from REP cycle

REPE

chain instruction

Repeat following CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 1 (result is Equal), maximum CX times.

Algorithm:

check_cx:

if CX <> 0 then

do following chain instruction
CX = CX - 1
if ZF = 1 then:
- go back to check_cx
else
- exit from REPE cycle

else

exit from REPE cycle

Example:
see cmpsb.asm in Samples.

REPNE

chain instruction

Repeat following CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 0 (result is Not Equal), maximum CX times.

Algorithm:

check_cx:

if CX <> 0 then

do following chain instruction
CX = CX - 1
if ZF = 0 then:
- go back to check_cx
else
- exit from REPNE cycle

else

exit from REPNE cycle

REPNZ

chain instruction

Repeat following CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 0 (result is Not Zero), maximum CX times.

Algorithm:

check_cx:

if CX <> 0 then

do following chain instruction
CX = CX - 1
if ZF = 0 then:
- go back to check_cx
else
- exit from REPNZ cycle

else

exit from REPNZ cycle

REPZ

chain instruction

Repeat following CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 1 (result is Zero), maximum CX times.

Algorithm:

check_cx:

if CX <> 0 then

do following chain instruction
CX = CX - 1
if ZF = 1 then:
- go back to check_cx
else
- exit from REPZ cycle

else

exit from REPZ cycle

RET

No operands
or even immediate

Return from near procedure.

Algorithm:

Pop from stack:
- IP
if immediate operand is present: SP = SP + operand

Example:

C	Z	S	O	P	A
unchanged

RETF

No operands
or even immediate

Return from Far procedure.

Algorithm:

Pop from stack:
- IP
- CS
if immediate operand is present: SP = SP + operand

C	Z	S	O	P	A
unchanged

ROL

memory, immediate
REG, immediate

memory, CL
REG, CL

Rotate operand1 left. The number of rotates is set by operand2.

Algorithm:

shift all bits left, the bit that goes off is set to CF and the same bit is inserted to the right-most position.

Example:

C	O
r	r

OF=0 if first operand keeps original sign.

ROR

memory, immediate
REG, immediate

memory, CL
REG, CL

Rotate operand1 right. The number of rotates is set by operand2.

Algorithm:

shift all bits right, the bit that goes off is set to CF and the same bit is inserted to the left-most position.

Example:

C	O
r	r

OF=0 if first operand keeps original sign.

SAHF

No operands

Store AH register into low 8 bits of Flags register.

Algorithm:

flags register = AH

bits 1, 3, 5 are reserved.

C	Z	S	O	P	A
r	r	r	r	r	r

SAL

memory, immediate
REG, immediate

memory, CL
REG, CL

Shift Arithmetic operand1 Left. The number of shifts is set by operand2.

Algorithm:

Shift all bits left, the bit that goes off is set to CF.
Zero bit is inserted to the right-most position.

Example:

C	O
r	r

OF=0 if first operand keeps original sign.

SAR

memory, immediate
REG, immediate

memory, CL
REG, CL

Shift Arithmetic operand1 Right. The number of shifts is set by operand2.

Algorithm:

Shift all bits right, the bit that goes off is set to CF.
The sign bit that is inserted to the left-most position has the same value as before shift.

Example:

C	O
r	r

OF=0 if first operand keeps original sign.

SBB

REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate

Subtract with Borrow.

Algorithm:

operand1 = operand1 - operand2 - CF

Example:

C	Z	S	O	P	A
r	r	r	r	r	r

SCASB

No operands

Compare bytes: AL from ES:[DI].

Algorithm:

ES:[DI] - AL
set flags according to result:
OF, SF, ZF, AF, PF, CF
if DF = 0 then
- DI = DI + 1
else
- DI = DI - 1

C	Z	S	O	P	A
r	r	r	r	r	r

SCASW

No operands

Compare words: AX from ES:[DI].

Algorithm:

ES:[DI] - AX
set flags according to result:
OF, SF, ZF, AF, PF, CF
if DF = 0 then
- DI = DI + 2
else
- DI = DI - 2

C	Z	S	O	P	A
r	r	r	r	r	r

SHL

memory, immediate
REG, immediate

memory, CL
REG, CL

Shift operand1 Left. The number of shifts is set by operand2.

Algorithm:

Shift all bits left, the bit that goes off is set to CF.
Zero bit is inserted to the right-most position.

Example:

C	O
r	r

OF=0 if first operand keeps original sign.

SHR

memory, immediate
REG, immediate

memory, CL
REG, CL

Shift operand1 Right. The number of shifts is set by operand2.

Algorithm:

Shift all bits right, the bit that goes off is set to CF.
Zero bit is inserted to the left-most position.

Example:

C	O
r	r

OF=0 if first operand keeps original sign.

STC

No operands

Set Carry flag.

Algorithm:

CF = 1

STD

No operands

Set Direction flag. SI and DI will be decremented by chain instructions: CMPSB, CMPSW, LODSB, LODSW, MOVSB, MOVSW, STOSB, STOSW.

Algorithm:

DF = 1

STI

No operands

Set Interrupt enable flag. This enables hardware interrupts.

Algorithm:

IF = 1

STOSB

No operands

Store byte in AL into ES:[DI]. Update SI.

Algorithm:

ES:[DI] = AL
if DF = 0 then
- DI = DI + 1
else
- DI = DI - 1

Example:

C	Z	S	O	P	A
unchanged

STOSW

No operands

Store word in AX into ES:[DI]. Update SI.

Algorithm:

ES:[DI] = AX
if DF = 0 then
- DI = DI + 2
else
- DI = DI - 2

Example:

C	Z	S	O	P	A
unchanged

SUB

REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate

Subtract.

Algorithm:

operand1 = operand1 - operand2

Example:

C	Z	S	O	P	A
r	r	r	r	r	r

TEST

REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate

Logical AND between all bits of two operands for flags only. These flags are effected: ZF, SF, PF. Result is not stored anywhere.

These rules apply:

1 AND 1 = 1
1 AND 0 = 0
0 AND 1 = 0
0 AND 0 = 0

Example:

C	Z	S	O	P
0	r	r	0	r

XCHG

REG, memory
memory, REG
REG, REG

Exchange values of two operands.

Algorithm:

operand1 < - > operand2

Example:

C	Z	S	O	P	A
unchanged

XLATB

No operands

Translate byte from table.
Copy value of memory byte at DS:[BX + unsigned AL] to AL register.

Algorithm:

AL = DS:[BX + unsigned AL]

Example:

C	Z	S	O	P	A
unchanged

XOR

REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate

Logical XOR (Exclusive OR) between all bits of two operands. Result is stored in first operand.

These rules apply:

1 XOR 1 = 0
1 XOR 0 = 1
0 XOR 1 = 1
0 XOR 0 = 0

Example:

C	Z	S	O	P	A
0	r	r	0	r	?

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