zynqmp pl端eth phy选用ar8035
zynqmp pl选用 ar8035
zynqmp的ps端链接ar8035phy时只需要更改dts，增加rgmii-id的方式即可
&gem0 {
status = "okay";
local-mac-address = [00 00 12 34 56 70];
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem0_default>;
phy1: phy@4 {
reg = <4>;
};
};
但是如果通过pl的axi eth tri mode链接ar8035时，只更改此项是不可以的，通过内核部分的打印，和查看内核的源码很容易就可以看到 axi的驱动并没有增加delay的支持
因此需要更改内核代码
在xilinx_axienet_mdio.c中的axienet_mdio_setup函数添加
实际上就是调整phy侧的delay来适应，4是我的板子上的phy addr
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
index 55c0ea9..4d9bbb8 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
@@ -72,6 +72,8 @@ static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg)
dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n",
phy_id, reg, rc);
+ printk("axienet_mdio_read(phy_id=%i, reg=%x) == %x\n",
+ phy_id, reg, rc);
return rc;
}
@@ -96,7 +98,8 @@ static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
phy_id, reg, val);
-
+ printk("axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
+ phy_id, reg, val);
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
return ret;
@@ -222,6 +225,16 @@ int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np)
lp->mii_bus = bus;
ret = of_mdiobus_register(bus, np1);
+
+ printk("axienet_mdio_setup in \r\n");
+
+ axienet_mdio_read(bus, 4, 0x1d);
+ axienet_mdio_write(bus, 4, 0x1d, 0x0b);
+ axienet_mdio_read(bus, 4, 0x1d);
+ axienet_mdio_read(bus, 4, 0x1e);
+ axienet_mdio_write(bus, 4, 0x1e, 0xbc00);
+ axienet_mdio_read(bus, 4, 0x1e);
+
if (ret) {
mdiobus_free(bus);
lp->mii_bus = NULL;
重新 build 上板，调试通过