发一个用状态机实现的按键检测是VERILOG代码

 

module key_det(
input clk,rst,
input key,
output reg  key_down,key_up
);

`define CNTR_MAX (1000*1000*10)
`define ACT_LEVEL  0

reg [31:0]d ;
reg[10:0]st ;

always @(posedge clk)if (st==1)d<=d+1;else d<=0;

always @(posedge clk)
if (rst)st<=0;else
case (st)
0: if (key==`ACT_LEVEL) st<=1;
1: if (d>=`CNTR_MAX)st<=2;
2: st<=3;
3: if (key!=`ACT_LEVEL)st<=4;
4: st<=0;
default st<=0;
endcase

always @ (posedge clk) key_down <= st == 2 ;
always @ (posedge clk) key_up <= st == 4;
 
endmodule