STM8S（105K4）使用笔记——系统时钟的基础配置

0、STM8s105在系统复位后默认开启HSI，同时进行8分频

可以通过查看
寄存器CLK_ICKR为0x03（HSI使能）
寄存器CLK_CKDIVR为0x18（HSI分频为8分频）

1、初始化

使能HSI（系统初始化后HSI默认使能）

	CLK->ICKR |= 0x01;		

禁用HSI

	CLK->ICKR &= (uint8_t)(~0x01);

使能LSI（若需要使用awu，请使能LSI）

	CLK->ICKR |= 0x08;

禁用LSI

	CLK->ICKR &= (uint8_t)(~0x08);

2、时钟分频

a、主时钟分频

1分频

CLK->CKDIVR &= (uint8_t)(~0x18);
CLK->CKDIVR |= (uint8_t)0x00;

2分频

CLK->CKDIVR &= (uint8_t)(~0x18);
CLK->CKDIVR |= (uint8_t)0x08;

4分频

CLK->CKDIVR &= (uint8_t)(~0x18);
CLK->CKDIVR |= (uint8_t)0x10;

8分频

CLK->CKDIVR &= (uint8_t)(~0x18);
CLK->CKDIVR |= (uint8_t)0x18;

b、CPU时钟分频（系统时钟分频）

1分频

CLK->CKDIVR &= (uint8_t)(~0x07);
CLK->CKDIVR |= (uint8_t)((uint8_t)0x80 & (uint8_t)0x07);

2分频

CLK->CKDIVR &= (uint8_t)(~0x07);
CLK->CKDIVR |= (uint8_t)((uint8_t)0x81 & (uint8_t)0x07);

4分频

CLK->CKDIVR &= (uint8_t)(~0x07);
CLK->CKDIVR |= (uint8_t)((uint8_t)0x82 & (uint8_t)0x07);

8分频

CLK->CKDIVR &= (uint8_t)(~0x07);
CLK->CKDIVR |= (uint8_t)((uint8_t)0x83 & (uint8_t)0x07);

16分频

CLK->CKDIVR &= (uint8_t)(~0x07);
CLK->CKDIVR |= (uint8_t)((uint8_t)0x84 & (uint8_t)0x07);

32分频

CLK->CKDIVR &= (uint8_t)(~0x07);
CLK->CKDIVR |= (uint8_t)((uint8_t)0x85 & (uint8_t)0x07);

64分频

CLK->CKDIVR &= (uint8_t)(~0x07);
CLK->CKDIVR |= (uint8_t)((uint8_t)0x86 & (uint8_t)0x07);

128分频

CLK->CKDIVR &= (uint8_t)(~0x07);
CLK->CKDIVR |= (uint8_t)((uint8_t)0x87 & (uint8_t)0x07);

3、初始化案例

/**
  * @brief  CLK Initialization Function
  * @param  None
  * @retval None
  * @par    HSI 16Mhz,LSI 128Khz
  */
static void _CLK_Init(void)
{
  /* Enable Internal High Speed Pscillator (HSI) for cpu & peripherals */
  CLK->ICKR |= 0x01;

  /* Enable Internal Low Speed Pscillator (LSI) for iwdg & awu */
  CLK->ICKR |= 0x08;

  /* Configure the Fmaster to DIV1 ,the default DIV of Fmaster if DIV8 */
  CLK->CKDIVR &= (uint8_t)(~0x18);
  CLK->CKDIVR |= (uint8_t)0x18;

  /* Configure the Fcpu to DIV1 */
  CLK->CKDIVR &= (uint8_t)(~0x07);
  CLK->CKDIVR |= (uint8_t)((uint8_t)0x80 & (uint8_t)0x07);
}