Verilog Code

// Verilog Module exam.bcdsub
//

// Created:
//          by - kingbeful
//          at - 12:35:19 2007-01-25
//
`resetall
`timescale 1ns/10ps
module bcdsub(a, b, sub, dout);
  input[11:0] a;
  input[11:0] b;
 
  output[11:0] sub;
  output dout;
 
  wire[2:0] d;
  wire[11:0] m1,m2;
  wire[7:0] m3;
  wire[7:0] m4;
  wire[11:0] sub;

// ### Please start your Verilog code here ###

//sub4 (a,b,din,dout,sub);

sub4 u1(m1[3:0],m2[3:0],1'b0,d[0],m3[3:0]);
sub4 u2(m1[7:4],m2[7:4],d[0],d[1],m3[7:4]);
sub4 u3(m1[11:8],m2[11:8],d[1],d[2],sub[11:8]);
//add4(a, b, sum);
add4 u4(m3[3:0],4'b1010,m4[3:0]);
add4 u5(m3[7:4],4'b1010,m4[7:4]);
 
assign dout = a >= b?0:1;           
assign m1 = dout?b:a;
assign m2 = dout?a:b;
assign sub[3:0] = d[0]?m4[3:0]:m3[3:0];
assign sub[7:4] = d[1]?m4[7:4]:m3[7:4];

endmodule

module add4(a, b, sum);
input [3:0] a, b;
output [3:0] sum;

assign sum = a + b;

endmodule

`resetall
`timescale 1ns/10ps
module sub4 (a,b,din,dout,sub);
  input[3:0] a;
  input[3:0] b;
  input din;
 
  output dout;
  output[3:0] sub;
 
  wire dout;
  wire[3:0] sub;

// ### Please start your Verilog code here ###
//always @ (a or b or din)
assign  {dout,sub} = a - b - din;

endmodule

 

//
// Verilog Module exam.fsm
//
// Created:
//          by - kingbeful
//          at - 12:17:43 2007-01-25
//

 

`resetall
`timescale 1ns/10ps
module fsm(clk, clear, cutlow, cutover, reset, std_f_sel);
 
  input clk;
  input clear;
  input cutlow;
  input cutover;
 
  output [1:0] std_f_sel;
  output reset;
  
  reg [1:0] std_f_sel;
  reg [2:0] state;
  reg reset;
  // ### Please start your Verilog code here ###
  parameter state_a=0, state_b=1, state_c=2, state_d=3, state_e=4, state_f=5;
  
always @(state)
begin
  case (state)
  state_a:
    begin
      reset = 1;
      std_f_sel = 2'b00;
    end
  state_b:
    begin
      reset = 0;
      std_f_sel = 2'b00;
    end
  state_c:
    begin
      reset = 1;
      std_f_sel = 2'b01;
    end
  state_d:
    begin
      reset = 0;
      std_f_sel = 2'b01;
    end
  state_e:
    begin
      reset = 1;
      std_f_sel = 2'b11;
    end
state_f:
    begin
      reset = 0;
      std_f_sel = 2'b11;
    end                
endcase
end

always @(posedge clk or posedge clear)
begin
  if (clear)
    state = state_c;
  else
    case (state)
      state_a:
        state = state_b;
      state_b:
        if (cutlow)
          state = state_c;
        else
          state = state_b;
      state_c:
        state = state_d;
      state_d:
        begin
          if (cutlow)
            state = state_e;
          else if (cutover)
            state = state_a;
          else
            state = state_d;
        end
      state_e:
        state = state_f;
      state_f:
        if (cutover)
          state = state_c;
        else
          state = state_f;
    endcase
end
  
endmodule

 

 

 

//
// Verilog Module exam.timer
//
// Created:
//          by - kingbeful
//          at - 09:43:04 2007-01-25
//

 

`resetall
`timescale 1ns/10ps
module timer(clk,clr,pause,min,sec,cent_sec);
  input clk;
  input clr;
  input pause;
 
  output[5:0] min;
  output[5:0] sec;
  output[6:0] cent_sec;  
 
  reg[5:0] min; 
  reg[5:0] sec;
  reg[6:0] cent_sec;
// ### Please start your Verilog code here ###

always @ (posedge clk or posedge clr)
 if (clr)
  begin
   min = 6'b000000;
      sec = 6'b000000;
      cent_sec = 7'b0000000;
  end
 else if (pause == 0)
  begin
   cent_sec = cent_sec + 1;
   if (cent_sec ==  7'b1100100)
    begin
     cent_sec = 0;
     sec = sec + 1;
    end 
   else
    cent_sec = cent_sec;
   if (sec == 6'b111100)
    begin
     sec = 0;
     min = min + 1;
    end
   else
    sec = sec;
   if (min == 6'b111100)
       min = 0;
      else
       min = min;
  end
 else
  cent_sec = cent_sec; 
endmodule