module paral1(q,a,clk);
output q,a;
input clk;
reg q,a;
initial q<=0;
always @(posedge clk)
begin
q=~q;
end
always @(posedge clk)
begin
a=~q;
end
endmodule
`timescale 1ns / 1ns
module paral_tst(
);
wire q,a;
reg clk;
paral1 u1(.q(q),.a(a),.clk(clk));
initial clk<=1'b0;
always #10 clk<=~clk;
endmodule
module paral2(
q,a,clk
);
output q,a;
input clk;
reg q,a;
initial q<=0;
always @(posedge clk)
begin
a=~q;
end
always @(posedge clk)
begin
q=~q;
end
endmodule
`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2020/02/24 12:04:54
// Design Name:
// Module Name: tst
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tst(
);
wire a,q;
reg clk;
paral2 u1 (.clk(clk),.a(a),.q(q));
initial begin
clk<=1'b0;
end
always #10 clk<=~clk;
endmodule
