S3C2440-Datasheet

S3C2440用的是ARM920T开发的，采用AMBA：增强微控制的哈佛总线架构。

什么是哈佛总线结构呢，及数据和程序分开.

S3C2440里有独立的16KB的数据缓存+16KB的指令缓存。

·  Around 1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB DCache/MMU

·  External memory controller (SDRAM Control and Chip Select logic)
·  LCD controller (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA
·  4-ch DMA controllers with external request pins
·  3-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)
·  2-ch SPls
·  IIC bus interface (multi-master support)
·  IIS Audio CODEC interface
·  AC’97 CODEC interface
·  SD Host interface version 1.0 & MMC Protocol version 2.11 compatible
·  2-ch USB Host controller / 1-ch USB Device controller (ver 1.1)
·  4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer
·  8-ch 10-bit ADC and Touch screen interface
·  RTC with calendar function
·  Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for scaling)
·  130 General Purpose I/O ports / 24-ch external interrupt source
·  Power control: Normal, Slow, Idle and Sleep mode

·  On-chip clock generator with PLL

Architecture
·  Integrated system for hand-held devices and general embedded applications.
·  16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core.
·  Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux.
·  Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance.
·  ARM920T CPU core supports the ARM debug architecture.
·  Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB).

System Manager
·  Little/Big Endian support.
·  Support Fast bus mode and Asynchronous bus mode.
·  Address space: 128M bytes for each bank (total 1G bytes).
·  Supports programmable 8/16/32-bit data bus width for each bank.
·  Fixed bank start address from bank 0 to bank 6.
·  Programmable bank start address and bank size for bank 7.
·  Eight memory banks:
– Six memory banks for ROM, SRAM, and others.
– Two memory banks for ROM/SRAM/ Synchronous DRAM.
·  Complete Programmable access cycles for all memory banks.
·  Supports external wait signals to expand the bus cycle.
·  Supports self-refresh mode in SDRAM for powerdown.
·  Supports various types of ROM for booting (NOR/NAND Flash, EEPROM, and others).

NAND Flash Boot Loader
·  Supports booting from NAND flash memory.
·  4KB internal buffer for booting.
·  Supports storage memory for NAND flash memory after booting.
·  Supports Advanced NAND flash

Cache Memory
·  64-way set-associative cache with I-Cache (16KB) and D-Cache (16KB).
·  8words length per line with one valid bit and two dirty bits per line.
·  Pseudo random or round robin replacement algorithm.
·  Write-through or write-back cache operation to update the main memory.
·  The write buffer can hold 16 words of data and four addresses.

Clock & Power Manager
·  On-chip MPLL and UPLL: UPLL generates the clock to operate USB Host/Device.
MPLL generates the clock to operate MCU at
maximum 400Mhz @ 1.3V.
·  Clock can be fed selectively to each function block
by software.
·  Power mode: Normal, Slow, Idle, and Sleep
mode
Normal mode: Normal operating mode
Slow mode: Low frequency clock without PLL
Idle mode: The clock for only CPU is stopped.
Sleep mode: The Core power including all
peripherals is shut down.
·  Woken up by EINT[15:0] or RTC alarm interrupt
from Sleep mode