T触发器

module cy4(input T,
           input clk,
           input rst_n,
           output reg Q
        );
always @(posedge clk or negedge rst_n)
  if(!rst_n) Q <= 1'b0;
  else if(T == 1) Q <= ~Q;
  else if(T == 0) Q <= Q;
  else;
endmodule

测试脚本代码：
`timescale 1 ns/ 1 ps
module cy4_vlg_tst();
reg T;
reg clk;
reg rst_n;
wire Q;
cy4 i1 (
.Q(Q),
.T(T),
.clk(clk),
.rst_n(rst_n)
);
initial
begin
clk = 0;
rst_n = 0;

10;

rst_n = 1;
T = 0;

10;

T = 1;

10;

stop; s t o p ; display(“Running testbench”);
end
always #20 clk = ~clk;
endmodule