scard2
ISO 7816(1-3) Smart Card Standard(二)
When informations exchange is terminated or aborted (unresponsive card or detection of card removal), the electrical contacts shall be desactivated.
The deactivation by the interface device shall consist of the consecutive operations:
- State L on RST;
- State L on CLK;
- Vpp inactive;
- State A on I/O;
- VCC inactive;
ISO7816 3.3 Answer to Reset
Two types of transmissions are considered:
* Asynchronous transmission:
In this type of transmission, characters are transmitted on the I/O line in an asynchronous half duplex mode. Each character includes an 8bit byte.
* Synchronous transmission:
In this type of transmission, a series of bits is transmitted on the I/O line in half duplex mode in synchronisation with the clock signal on CLK.
ISO7816 3.1.a - Answer to Reset in asynchronous transmission
* Bit duration
""""""""""""
The nominal bit duration used on I/O is defined as one Elementary Time Unit (etu).
For cards having internal clock, the initial etu is 1/9600 s.
For cards using the external clock, there is a linear relationship between the Elementary Time Unit used on I/O and the period provided by the interface device on CLK.
The initial etu is 372/fi s where fi is in Hertz.
The initial frequency fi is provided by the interface device on CLK during the Answer to Reset.
In order to read the initial character (TS), all cards shall initially be operated with fi in the range of 1 MHz to 5 MHz.
* Character frame during answer to reset
""""""""""""""""""""""""""""""""""""""
Prior to the transmission of a character, I/O shall be in state Z.
A character consists of ten consecutive bits:
- a start bit in state A;
- eight bits of information, designated ba to bh and conveying a data byte;
- a tenth bit bi used for even parity checking.
A data byte consists of 8 bits designated b1 to b8, from the least significant bit (lsb, b1) to the most significant bit (msb, b8).
Conventions (level coding, connecting levels Z/A to digits 1 or 0: and a bit significance, connecting ba...bh to b1...b8) are specified in the initial character, call TS, which is transmitted by the card in response to reset.
Parity is correct when the number of ONES is even in the sequence from ba to bi.
Whithin a character, the time from the leading edge of the start bit to the trailing edge of the nth bit shall equal (n+/-0.2) etu.
When searching for a start, the receiver samples I/O periodically. The time origin being the mean between last observation of level Z and first observation of level A, the start shall be verified before 0.7 etu, and then ba is received at (1.5 +/-0.2) etu. Parity is checked on the fly.
NOTE : When searching for a start, the sampling time shall be less than 0.2 etu so that all the test zones are distinct from the transition zones.
The delay between two consecutives characters (between start leading edges) is at least 12 etu, including a character duration (10+/-0.2) etu plus a guardtime, the interface device and the card reamain both in reception, so that I/O is in state Z.
Start Parity Next
bit <----- 8 data bits -----> bit Start bit
Z ____ ________________________________......______ __
| | | | | | | | | | | | |
I/O | |ba|bb|bc|bd|be|bf|bg|bh|bi| Guardtime | |
|___|__|__|__|__|__|__|__|__|__| |___|_
A : : : :
0 t1 : t10
: :
:<---- (n+/-0.2) etu --->:
Figure 3: Character frame
During the Answer to Reset, the delay between the start leading edges of two consecutives characters from the card shall not exeed 9600 etu. This maximum is named initial waiting time.
* Error detection and character repetition
""""""""""""""""""""""""""""""""""""""""
During the answer to reset, the following characters repetition procedure depends on the protocol type. This procedure is mandatory for cards using the protocol type T=0; it is optional for the interface device and for the other cards.
The transmitter tests I/O (11+/-0.2) etu after the start leading edge:
- If I/O is in state Z, the correct reception is assumed.
- If I/O is in state A, the transmission is assumed to have been incorrect. The disputed character shall be repeated after a delay of at least 2 etu after detection of the error signal.
When parity is incorrect, from (10.5+/-0.2) etu, the receiver transmits an error signal at state A for 1 etu minimum and 2 etu maximum. The receiver then shall expect a repetition of the disputed character (see figure 8).
If no character repetition is provided by the card, - The card ignores and shall not suffer damage from the error signal coming from the interface device.
- The interface device shall be able to initiate the reception and the whole Answer to Reset response sequence.
* Structures and content
""""""""""""""""""""""
A reset operation results in the answer from the card consisting of the initial character TS followed by at most 32 characters in the following order:
- T0 ................... Format character (Mandatory)
- TAi, TBi, TCi, TDi ... Interface characters (Optional)
- T1, T2, ... ,TK ...... Historical characters (Optional)
- TCK .................. Check character (Conditional)
Reset
|
| _________________________________________ _______ _________
| | | | | | | | | | | | | | | | |
'-->| TS| T0|TA1|TB1|TC1|TD1|TA2|TB2|TC2|TD2| ......... | T1| ... | TK|TCK|
|___|___|___|___|___|___|___|___|___|___|_ _|___|_ _|__ |___|
TS : Initial character
TO : Format character
TAi : Interface character [ codes FI,DI ]
TBi : Interface character [ codes II,PI1 ]
TCi : Interface character [ codes N ]
TDi : Interface character [ codes Yi+1, T ]
T1, ... , TK : Historical characters (max,15)
TCK : Check character
Figure 4 : General configuration of the Answer to Reset
The interface characters specify physical parameters of the integrated circuit in the card and logical characteristics of the subsequent exchange protocol.
The historical characters designate general information, for example, the card manufacturer, the chip inserted in the card, the masked ROM in the chip, the state of the life of the card. The specification of the historical characters falls outside the scope of this part of ISO/IEC7816.
For national simplicity, T0, TAi, ... ,TCK will designate the bytes as well as the characters in which they are contained.
Structure of TS, the initial character
--------------------------------------
The initial character TS provides a bit shynchronisation sequence and defines the conventions to code data bytes in all subsequent characters. These conventions refer to ISO1177.
I/O is initially in state Z. A bit synchronisation sequence (Z)AZZA is defined for the start bit and bits ba bb bc (see figure 5).
The last 3 bits bg bh bi shall be AAZ for checking parity.
NOTE : This allows the interface device to determinate the etu initially used by the card. An alternate measurement of etu is a third of the delay between the first two falling edges in TS. Transmission and reception mechanisms in the card shall be consistent with the alternate
definition of etu.
The two possible values of TS (ten consecutive bits from start to bi and corresponding hexadecimal value) are
- Inverse convention : (Z)ZZAAAAAZ
where logic level ONE is A, ba is b8 (msb is first), equal to $3F when decoded by inverse convention.
- Direct convention : (Z)ZZAZZZAAZ
where logic level ONE is Z, ba is b1 (lsb first), equal to $3B when decoded by direct convention.
Start ba bb bc bd be bf bg bh bi
Z ____ _______ ___________ ______
| | | | | Z Z Z | | | |
(Z)| A | Z Z | A | or | | Z (Z)
A |___| |___|_A___A___A_|___|___|
Figure 5 : Initial character TS
--------
Structure of the subsequent characters in the Answer to Reset
-------------------------------------------------------------
The initial character TS is followed by a variable number of subsequent characters in the following order: The format character T0 and, optionally the interface characters TAi, TBi, TCi, TDi and the
historical characters T1, T2, ... , TK and conditionally, the check character TCK.
The presence of the interface characters is indicated by a bit map technique explained below.
The presence of the historical characters is indicated by the number of bytes as specified in the format character defined below.
The presence of the check character TCK depends on the protocol type(s) as defined as below.
- Format character T0
-------------------
The T0 character contains two parts:
- The most significant half byte (b5, b6, b7, b8) is named Y1 and indicates with a logic level ONE the presence of subsequent characters TA1, TB1, TC1, TD1 respectively.
- The least significant half byte (b4 to b1) is named K and indicates the number (0 to 15) of historical characters.
,----,----,----,----,----,----,----,----,
| b8 | b7 | b6 | b5 | b4 | b3 | b2 | b1 |
'----'----'----'----'----'----'----'----'
:<------- Y1 ------>:<-------- K ------>:
Y1 : indicator for the presence of the interface characters
TA1 is transmitted when b5=1
TB1 is transmitted when b6=1
TC1 is transmitted when b7=1
TD1 is transmitted when b8=1
K : number of hitorical characters
Figure 6 : Informations provided by T0
--------
- Interface characters TAi, TBi, TCi, TDi
---------------------------------------
TAi, TBi, TCi (i=1, 2, 3, ... ) indicate the protocol parameters.
TDi indicates the protocol type T and the presence of subsequent
characters.
Bits b5, b6, b7, b8 of the byte containing Yi (T0 contains Y1; TDi contains Yi+1) state whelther character TAi for b5, character TBi for b6, character TCi for b7, character TDi for b8 are or are not (depending on whether the relevant bit is 1 or 0) transmitted subsequently in this
order after the character containing Yi.
When needed, the interface device shall attribute a default value to information corresponding to a non transmitted interface character.
When TDi is not transmitted, the default value of Yi+1 is null, indicating that no further interface characters TAi+j, TBi+j, TCi+j, TDi+j will be transmitted.
,----,----,----,----,----,----,----,----,
| b8 | b7 | b6 | b5 | b4 | b3 | b2 | b1 |
'----'----'----'----'----'----'----'----'
:<------ Yi+1 ----->:<------- T ------->:
Yi+1 : indicator for the presence of the interface characters
TAi+1 is transmitted when b5=1
TBi+1 is transmitted when b6=1
TCi+1 is transmitted when b7=1
TDi+1 is transmitted when b8=1
T : Protocol type for subsequent transmission.
Figure 7 : Informations provided by TDi
--------
- Historical characters T1, T2, ... ,TK
-------------------------------------
When K is not null, the answer to reset is continued by transmitting K historical characters T1, T2, ... , TK.
- Check character TCK
-------------------
The value of TCK shall be such that the exclusive-oring of all bytes from T0 to TCK included is null.
The answer to reset is complete 12 etu after the leading edge of the last character.
Protocol type T
---------------
The four least significant bits of any interface character TDi indicate a protocol type T, specifying rules to be used to process transmission protocols. When TDi is not transmitted, T=0 is used.
T=0 is the asynchronous half duplex character transmission protocol.
T=1 is the asynchronous half duplex block transmission protocol.
T=2 and T=3 are reserved for future full duplex operations.
T=4 is reserved for an enhanced asynchronous half duplex character
transmission protocol.
T=5 to T=13 are reserved for future use.
T=14 is reserved for protocols standardized by ISO.
T=15 is reserved for future extension.
NOTE : If only T=0 is indicated, TCK shall not be sent. In all other cases TCK shall be sent.
Specifications of the global interface bytes
--------------------------------------------
Among the interface bytes possibly transmitted by the card in answering to reset, this subclaus defines only the global interface bytes TA1,TB1, TC1, TD1.
These global interface bytes convey information to determine parameters which the interface device shall take into account.
- Parameters F, D, I, P, N
------------------------
This initial etu is used during answer to reset is replaced by the work etu during subsequent transmission. F is the clock rate conversion factor and D is the bit rate adjustment factor to determine the work etu in subsequent transmissions.
For internal clock cards:
initial etu = 1/9600 s work etu = (1/D)*(1/9600) s
For external clock cards:
initial etu = 372/fi s work etu = (1/D)*(F/fs) s
The minimum value of fs shall be 1MHz.
The maximum value of fs is given by table 6.
I and P define the active state at VPP.
- Maximum programming current : Ipp = 1mA
- Programming voltage : Vpp = P.V
N is an extra guardtime requested by the card. Before receiving the next character, the card requires a delay of at least (12+N) etu from the start leading edge of the previous character. No extra guardtme is used to send characters from the card to the interface device.
The default values of these parameters are:
F = 372 ; D = 1 ; I = 50 ; P = 5 ; N = 0
- Integer values in global interface bytes
----------------------------------------
The global interface bytes, TA1, TB1, TC1, TB2 code integer values FI, DI II, PI1, N, PI2 which are either equal to or used to compute the values of the parameters F, D, I, P, N presented above.
TA1 codes FI over the most significant half byte (b8 to b5) and DI over the least significant half byte (b4 to b1).
TB1 codes II over the bits b7 and b6, and PI1 over the 5 least significant bits b5 to b1. The most significant bit b8 equals to 0.
NOTE : The interface device may ignore the bit b8 of TB1.
TC1 codes N over the eight bits (b8 to b1).
TB2 codes PI2 over the eight bits (b8 to b1).
Table 6: Clock rate conversion factor F
-------
----------------------------------------------------------------------
FI | 0000 0001 0010 0011 0100 0101 0110 0111
--------------+-------------------------------------------------------
F | Internal clk 372 558 744 1116 1488 1860 RFU
--------------+-------------------------------------------------------
fs (max) MHz | - 5 6 8 12 16 20 -
----------------------------------------------------------------------
---------------------------------------------------------------
FI | 1000 1001 1010 1011 1100 1101 1110 1111
--------------+------------------------------------------------
F | RFU 512 768 1024 1536 2048 RFU RFU
--------------+------------------------------------------------
fs (max) MHz | - 5 7.5 10 15 20 - -
---------------------------------------------------------------
RFU : Reserved for Future Use
Table 7: Bit rate afjustment factor D
-------
-------------------------------------------------------
DI | 0000 0001 0010 0011 0100 0101 0110 0111
------+------------------------------------------------
D | RFU 1 2 4 8 16 RFU RFU
-------------------------------------------------------
-------------------------------------------------------
DI | 1000 1001 1010 1011 1100 1101 1110 1111
------+------------------------------------------------
D | RFU RFU 1/2 1/4 1/8 1/16 1/32 1/64
-------------------------------------------------------
RFU : Reserved for Future Use
- Programming voltage factor P
----------------------------
PI1 from 5 to 25 gives the value of P in volts. PI1=0 indicates that VPP is connected in the card which generates an internal programming voltage from VCC. Other values of PI1 are reserved for future use.
When PI2 is present, the indication of PI1 should be ignores. PI2 from 50 to 250 gives the value of P in 0.1V. Other values of PI2 are reserved for future use.
Table 8 : Maximum programming current factor I
-------
-------------------------------
II | 00 01 10 11
-----+-------------------------
I | 25 50 100 RFU
-------------------------------
- Extra guardtime N
-----------------
N codes directly the extra guard time, from 0 to 254 etu. N=255 indicates that the minimum delay between the start edges of two consecutives characters is reduced to 11 etu.
ISO 7816(1-3) Smart Card Standard(一)
This part describes the physical charcteristics of integrated circuit cards. It includes accomodation of exposure limits for a number of electromagnetic phenomena such as X-rays, UV light, elacromagnetic fields, static electrical fields, and ambient temperature of the card.
Furthermore ISO7816-1 defines the characteristics of a card when it is bent or flexed. This is to make sure that plastic cards with embedded chips are manufactured in a way that guarantees flawless operation over the expected life time of a card. Connections beween the surface connectors and the I/O pins of the embedded silicon die must be maintaned and withstand mechanical stress. Bending and flexing procedures are standardised in ISO 7816.
This part of ISO7816 is important for card manufacturers. They are the ones that choose the materials and establish a process that embeds the integrated circuit into the card.
Part 2: Dimensions and Location of the Contacts
ISO 7816 part 2 defines the dimensions and location of the contacts. This part includes standards about number, function and position of the electrical contacts.
The integrated circuit card (ICC) has 8 electrical contacts . They are referred to as C1 through C8. However, not all 8 contacts are electrically connected to the embedded microprocessor chip and therefore unused at the present time.
The following table contains the contact definition according to ISO7816-2
| Contact | Designation | Use |
| C1 | Vcc | Power connection through which operating power is supplied to the microprocessor chip in the card |
| C2 | RST | Reset line through which the IFD can signal to the smart card's microprocessor chip to initiate its reset sequence of instructions |
| C3 | CLK | Clock signal line t hrough which a clock signal can be provided to the microprocessor chip. This line controls the operation speed and provides a common framework for data communication between the IFD and the ICC |
| C4 | RFU | Reserved for future use |
| C5 | GND | Ground line providing common electrical ground between the IFD and the ICC |
| C6 | Vpp | Programming power connection used to program EEPROM of first generation ICCs. |
| C7 | I/O | Input/output line that provides a half-duplex communication channel between the reader and the smart card |
| C8 | RFU | Reserved for future use |
Remark:
Some smart cards issued before 1990 were adherent to a different standard for the contact location and therefore can't be used with today's ISO7816-2 compliant smart card readers. These cards were deployed primarily in Europe.
Part 3: Electronic Signals and Transmission Protocols (1)
This part describes electronic signals and transmission protocols of integrated circuit cards. We copied it from a version that is available on the Internet. If you need the official version of this part, please contact ISO in switzerland.. If you have suggestions or material to include (tables, graphs etc) please contact us. The document will stay at this location for anyone that wants a direct link to this part of the standard. We will edit this document shortly, bring it up to date and add comments.
Most of ISO7816 3 is important for reader manufacturers or developers who want to establish a communication with a smart card on a very low level, the signal level. Going through ISO 7816-3 you will see what's involved in writing your own I/O software. This can be either to communicate from a microcontroller or a PC's serial/parallel/USB/PCMCIA port. Even if you don't go that far, it is quite interesting to read about what you can get out of an Answer to Reset (ATR).
There are many tools out there to read an ATR. Even on this site we put a remote version of a free ATR probing tool that reads and interprets an ATR over the Internet. All you need is a PCSC compliant smart card reader attached to a PC with an Internet connection.
Electrical Signals Description
I/O : Input or Output for serial data to the integrated circuit inside the card.
VPP : Programing voltage input (optional use by the card).
GND : Ground (reference voltage).
CLK : Clocking or timing signal (optional use by the card).
RST : Either used itself (reset signal supplied from the interface device) or in combination with an interal reset control circuit (optional use by the card). If internal reset is implemented, the voltage
supply on Vcc is mandatory.
VCC : Power supply input (optional use by the card).
NOTE - The use of th two remaining contacts will be defined in the appropriate application standards.
ISO7816 3.1 Voltage and current values
Abbreviations:
Vih : High level input voltage
Vil : Low level input voltage
Vcc : Power supply voltage at VCC
Vpp : Programming voltage at VPP
Voh : High level output voltage
Vol : Low level output voltage
tr : Rise time between 10% and 90% of signal amplitude
tf : Fall time between 90% and 10% of signal amplitude
Iih : High level input current
Iil : Low level input current
Icc : Supply current at VCC
Ipp : Programming current at VPP
Ioh : High level output current
Iol : Low level output current
Cin : Input capacitance
Cout: Output capacitance
* I/O
This contact is used as input (reception mode) or output (transmission mode) for data exchange. Two possible states exist for I/O:
- mark or high state (State Z), if the card and the interface device are in reception mode or if the state is imposed by the transmitter.
- space or low state (State A), if this state is imposed by the
transmitter.
When the two ends of the line are in reception mode, the line shall be maintained in state Z. When the two ends are in non-matced transmit mode, the logic state of the line may be indeterminate. During operations, the interface device and the card shall not both be in transmit mode.
Table 1 - Electrical characteristics of I/O under normal operation conditions.
,--------+--------------------------------+---------+---------+------, | Symbol | Conditions | Minimum | Maximum | Unit | +--------+--------+-----------------------+---------+---------+------+ | | Either | Iih max = +/- 500uA | 2 | VCC | V | | Vih | (1) +-----------------------+---------+---------+------+ | | or | Iih max = +/- 50uA | 0.7 VCC | VCC (3) | V | +--------+--------+-----------------------+---------+---------+------+ | Vil | Iil max = 1mA | 0 | 0.8 | V | +--------+--------------------------------+---------+---------+------+ | | Either | Iol max = +/- 100uA | 2.4 | VCC | V | | Voh | +-----------------------+---------+---------+------+ | (2) | or | Iol max = +/- 20uA | 3.8 | VCC | V | +--------+--------+-----------------------+---------+---------+------+ | Vol | Iol max = 1mA | 0 | 0.4 | V | +--------+--------------------------------+---------+---------+------+ | tr, tf | Cin = 30pF; Cout = 30pF | | 1 | us | +--------+--------------------------------+---------+---------+------+ | (1) For the interface device, take into account both conditions. | | (2) It is assumed that a pull up resistor is used in the interface | | device (recommended value 20k Ohm. | | (3) The voltage on I/O shall remain between 0.3V and VCC+0.3V. | '--------------------------------------------------------------------'
* VPP
This contact may be to supply the voltage required to program or to erase the internal non-volatile memory. Two possible states exists for VPP: Idle state and active state, as defined in table 2. The idle state shall be maintained by the interface device unless the active state is required.
Table 2 : Electrical characteristics of VPP under normal operation conditions.
,--------+--------------------------------+---------+---------+------, | Symbol | Conditions | Minimum | Maximum | Unit | +--------+--------------------------------+---------+---------+------+ | Vpp | Idle State | 0.95*Vcc| 1.05*Vcc| V | | Ipp | (programming non active) | | 20 | mA | +--------+--------------------------------+---------+---------+------+ | Vpp | Active State | 0.975*P | 1.025*P | V | | Ipp | (programming the card) | | I | mA | +--------+--------------------------------+---------+---------+------+ | The card provides the interface with the values of P and I | | (default values: P=5 and I=50) | '--------------------------------------------------------------------'
Rise of fall time : 200 us maximum. The rate of change of Vpp shall not exceed 2V/us.
The maximum power Vpp*Ipp shall not exceed 1.5W when averaged over any period of 1s.
* CLK
The actual frequency, delivered by the interface device on CLK, is designated either by fi the initial frequency during the answer to reset, or by fs the subsequent frequency during subsequent transmission.
Duty cycle for asynchronous operations shall be between 45% and 55% of the period during stable operation. Care shall be taken when switching frequencies (from fi to fs) to ensure that no pulse is shorter than 45% of the shorter period.
Table 3 - Electrical characteristics of CLK under normal operation conditions.
,--------+--------------------------------+---------+---------+------,
| Symbol | Conditions | Minimum | Maximum | Unit |
+--------+--------+-----------------------+---------+---------+------+
| | Either | Iih max = +/- 200uA | 2.4 | VCC (2) | V |
| | (1) +-----------------------+---------+---------+------+
| Vih | or | Iih max = +/- 20uA | 0.7*VCC | VCC (2) | V |
| | (1) +-----------------------+---------+---------+------+
| | or | Iih max = +/- 10uA | VCC-0.7 | VCC (2) | V |
+--------+--------+-----------------------+---------+---------+------+
| Vil | Iil max = +/-200 uA | 0 (2) | 0.5 | V |
+--------+--------------------------------+---------+---------+------+
| tr, tf | Cin = 30pF | |9% of the period|
| | | |with a max:0.5us|
+--------+--------------------------------+---------+---------+------+
| (1) For the interface device, take into account three conditions. |
| (2) The voltage on CLK shall remain between 0.3V and Vcc+0.3V. |
'--------------------------------------------------------------------'
* RST
Table 4 - Electrical characteristics of RST under normal operation conditions.
,--------+--------------------------------+---------+---------+------,
| Symbol | Conditions | Minimum | Maximum | Unit |
+--------+--------+-----------------------+---------+---------+------+
| | Either | Iih max = +/- 200uA | 4 | VCC (2) | V |
| Vih | (1) +-----------------------+---------+---------+------+
| | or | Iih max = +/- 10uA | VCC-0.7 | VCC (2) | V |
+--------+--------+-----------------------+---------+---------+------+
| Vil | Iil max = +/- 200uA | 0 (2) | 0.6 | V |
+--------+--------------------------------+---------+---------+------+
| (1) For the interface device, take into account both conditions. |
| (2) The voltage on RST shall remain between 0.3V and VCC+0.3V. |
'--------------------------------------------------------------------'
* VCC
This contact is used to supply the power voltage Vcc.
Table 5 - Electrical characteristics of VCC under normal operation conditions.
,--------+---------+---------+-------,
| Symbol | Minimum | Maximum | Unit |
+--------+---------+---------+-------+
| Vcc | 4.75 | 5.25 | V |
| Icc | | 200 | mA |
'--------+---------+---------+-------'
ISO7816 3.2 Operating procedure for integrated circuit(s) cards
This operating procedure applies to every integrated circuit(s) card with contacts:
The dialogue between the interface device and the the card shall be conducted through the consecutive operations:
- connection and activation of the contacts by the interface device.
- reset of the card.
- answer to reset by the card.
- subsequent information exchange between the card and the interface device.
- desactivation of the contacts by the interface device.
These operations are specified in the following subclauses.
NOTE :
An active state on VPP should not only be provided and maintained when requested by the card.
ISO7816 3.2.a - Connection and activation of the contacts
The electrical circuits shall not be activated until the contacts are connected to the interface device so as to avoid possible damage to any card meeting these standards.
The activation of the contacts by the interface device shall consist of the consecutive operations:
- RST is in state L;
- VCC shall be powered;
- I/O in the interface device shall be put in reception mode;
- VPP shall be raised to idle state;
- CLK shallbe provided with a suitable and stable clock.
ISO7816 3.2.b - Reset of the card
A card reset is initiated by the interface device, whereupon the card shall respond with an Answer to Reset as describe in 2.4.
By the end of the activation of the contacts (RST is in L, VCC powered and stable, I/O in reception mode in the interface device, VPP stable at idle level, CLK provided with a suitable and stable clock), the card answering asynchronously is ready for reset.
The clock signal is applied to CLK at time T0. The I/O line shall be set to state Z within 200 clcok cycles of the clock signal (t2) being applied to CLK (time t2 after T0).
An internally reset card reset after a few cycles of clock signal. The Answer to Reset on I/O shall begin between 400 and 40 000 clock cycles (t1) after the clock signal is applied to CLK (time t1 after T0).
A card with an active low reset is reset by maintaining RST in state L for at least 40 000 clock cycles (t3) after the clock signal is applied on CLK (time t3 after T0). Thus if no Answer to Reset begind within 40 000 clock cycles (t3) with RST in state L, RST is put to state H (at time T1). The
Answer to Reset on I/O shall begin between 400 and 40 000 clock cycles (t1) after the rising edge of the signal on RST (time t1 after T1).
If the Anwser to Reset does not begin within 40 000 clock cycles (t3) with RST in state H (t3 after T1), the signal on RST shall be returned to state L (at time T2) and the contacts shall be desactivated by the interface device.
GND ________________________________________________________________________
__________________________________________________________________
VCC _| : :|___
:_______________________________________________________________:
VPP __|: |____
: t3 t3 :
:<--------------------------->:<------------------------------->:
: :_________________________________:
RST ___:_____________________________| |____
: : :
CLK ___|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||____
: t1 : :
:<-------------->: : :
: __________:____________:_________________________________:
I/O __XXXXXXXX |____________:_______Answer____________________:XXXX
(IR) : : : :
: t2 : : t1 :
:<---->: :<---------->: :
: _______________________:_________________________________:
I/O __XXXXXXXX : |______Answer________:XXXX
(AL) : t2 : : :
:<---->: : :
: :_________________________________:
I/O __XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX: :XXXXX
(SH) : : :
T0 T1 T2
IR : Internal Reset t2 <= 200/fi
AL : Asynchronous Reset 400/fi <= t1 <= 40000/fi
SH : Syncronous Reset 40000/fi <= t3
Figure1 : Reset of the card
With a card answering synchonously, the interface device sets all the lines to state L (See figure 2). VCC is the powered, VPP is set to idle state, CLK and RST remain in L state, I/O is put in reception mode in the interface device, RST shall be maintained in state H for at least 50 us (t12), before returning to state L again.
The clock pulse is applied after an interval (t10) from the rising edge of the reset signal. The duration of the state H of the clock pulse can be any value between 10 us and 50 us ; no more than one clock pulse during reset high is allowed. The time interval between the falling edges on CLK
and RST is t11.
The first data bit is obtained as an answer to reset on I/O while CLK is in state L and is valid after an interval t13 from the falling edge on RST.
______________________________________________________________________
VCC__/
_____________________________________________________________________
VPP___/
t12
:<---------------->:
:__________________:
RST_____/: /_______________________________________________
: :
: t10 t11 : t15 t16
:<---->: :<---->: t14 :<---->: :<---->:
: ____ : :<---->: :______: : : _______
CLK_____________:/ 1 /:______:______:/ 2 /:______:/ 3 /_______
: :
: t13 : t17
:<---->: :<---->:
_____________________________ :______________ :______________ ___
I/O___///////////////////////////////:_______1______X-X_______2_______X-X___
5us <= t10 10us <= t14 <= 100us Clock low after RST
5us <= t11 10us <= t15 <= 50us Clock High
50us <= t12 ........ Reset High 10us <= t16 <= 100us Clock Low
t13 <= 10us Propagation delay t17 <= 10us Propagation delay
Figure2 : Reset of the card when a synchronous answer is expected.
NOTES:
1 - The internal state of the card is assumed not to be defined before reset. Therefore the design of the card has to avoid inproper operation.
2 - In order to continue the dialogue with the card, RST shall be maintained in the state where an answer occurs on I/O.
3 - Reset of a card can be initiated by the interface device at its discetion at any time.
4 - Interface devices may support one or more of these types of reset behaviour. The priority of testing for asynchronous or synchronous cards is not defined in this standard.
智能卡的操作系统——COS
1 COS概述
COS的全称是Chip Operating System(片内操作系统)，它一般是紧紧围绕着它所服务的智能卡的特点而开发的。由于不可避免地受到了智能卡内微处理器芯片的性能及内存容量的影响，因此，COS在很大程度上不同于我们通常所能见到的微机上的操作系统(例如DOS、UNIX等)。首先，COS是一个专用系统而不是通用系统。即：一种COS一般都只能应用于特定的某种(或者是某些)智能卡，不同卡内的COS一般是不相同的。因为coS一般都是根据某种智能卡的特点及其应用范围而特定设计开发的，尽管它们在所实际完成的功能上可能大部分都遵循着同一个国际标准。其次，与那些常见的微机上的操作系统相比较而言，COS在本质上更加接近于监控程序、而不是一个通常所谓的真正意义上的操作系统，这一点至少在目前看来仍是如此。因为在当前阶段，COS所需要解决的主要还是对外部的命令如何进行处理、响应的问题，这其中一般并不涉及到共享、并发的管理及处理，而且就智能卡在目前的应用情况而盲，并发和共享的工作也确实是不需要曲。COS在设计时一般都是紧密结合智能卡内存储器分区的情况，按照国际标准(ISO／IEC7816系列标准)中所规定的一些功能进行设计、开发。但是由于目前智能卡的发展速度很快，而国际标准的制定周期相对比较长一些，因而造成了当前的智能卡国际标准还不太完善的情况，据此，许多厂家又各自都对自己开发的COS作了一些扩充。就目前而言，还没有任何一家公司的CoS产品能形成一种工业标准。因此本章将主要结合现有的(指1994年以前)国际标准，重点讲述CO5的基本原理以及基本功能，在其中适当地列举它们在某些产品中的实现方式作为例子。
2 COS的体系结构
依赖于上一节中所描述的智能卡的硬件环境，可以设计出各种各样的cos。但是，所有的COS都必须能够解决至少三个问题，即：文件操作、鉴别与核实、安全机制。事实上，鉴别与核实和安全机制都属于智能卡的安全体系的范畴之中，所以，智能卡的coS中最重要的两方面就是文件与安全。但再具体地分析一下，则我们实际上可以把从读写设备(即接口设备IFD)发出命令到卡给出响应的一个完整过程划分为四个阶段，也可以说是四个功能模块：传送管理器(TM)、安全管理器(SM)、应用管理器(AM)和文件管理器(FM)，如图6．35中所示。其中，传送管理器用于检查信息是否被正确地传送。这一部分主要和智能卡所采用的通信协议有关；安全管理器主要是对所传送的信息进行安全性的检查或处理，防止非法的窃听或侵入；应用管理器则用于判断所接收的命令执行的可能性；文件管理器通过核实命令的操作权限，最终完成对命令的处理。对于一个具体的COS命令而言，这四个阶段并不一定都是必须具备的，有些阶段可以省略，或者是并人另一阶段中；但一般来说，具备这四个阶段的COS是比较常见的。以下我们将按照这四个阶段对COS进行较为详细的论述。
在这里需要提起注意的是，智能卡中的“文件”概念与我们通常所说的“文件”是有区别的。尽管智能卡中的文件内存储的也是数据单元或记录，但它们都是与智能卡的具体应用直接相关的。一般而言，一个具体的应用必然要对应于智能卡中的一个文件，因此，智能卡中的文件不存在通常所谓的文件共享的情况。而且，这种文件不仅在逻辑广必须是完整的，在物理组织上也都是连续的。此外，智能卡中的文件尽管也可以拥有文件名(FileN8me)，但对文件的标识依靠的是与卡中文件—一对应的文件标识符(F3te ldentifier)，而不是文件名。因为智能卡中的文件名是允许重复的，它在本质上只是文件的一种助记符，并不能完全代表莱个文件。
采用鉴别寄存器方式时，通常是在内存RAM中设置一个8位(或者是16位)长的区域作为鉴别用寄存器。这里的鉴别是指对安全控制密码的鉴别。鉴别用寄存器所反映的是智能卡在当前所处的安全状态。采用这种方式时，智能卡的每个文件的文件头(或者是文件描述器)中通常都存储有该文件能够被访问的条件，——般是包括读、写两个条件r分别用Cr、Cu表示)，这就构成了该文件的安全属性。而用户通过向智能卡输入安全密码．就可以改变卡的安全状态，这一过程我们j至常称为出示，这就是鉴别寄存器为式的安全机制。把上面的二方面结合起来，就能够对卡中文件的读写权限加以控制了。具体的操作机制我们以 PCOS为例加以描述。
(转自：≡中国电子技术信息网≡ 网址： www.EC66.com)
智能卡概论
2.逻辑加密卡 卡中的集成电路具有加密逻辑和ZEPROM。
3.CPU卡 卡中的集成电路包括中央处理器CPU、EEPROM、随机存储器RAM以及固化在只读存储器ROM中的片内操作系统COS(ChiPOperatingSystem)。
1．1．IC卡的接口设备
为了使用卡片，还需要有与IC卡配合工作的接口设备IFD(InterFace Device)，或称为读写设备。IFD可以是一个由微处理器、键盘、显示器与I／O接口组成的独立设备，该接口设备通过IC卡上的8个触点向IC卡提供电源井与IC卡相互交换信息。IFD也可以是一个简单的接口电路，IC卡通过该电路与通用微机相连接。无论是磁卡或IC卡，在卡上能存储的信息总是有限的，因此大部分信息需要存放在接口设备或计算机中。当用信用卡购物时，如在允许透支范围内，则可以先取走商品，事后再结算；如需一笔大款，则需经银行确认，授权于商店后，才能取走商品。由于银行、发放信用卡的公司以及商店不在同一处，因此需要经过通信线路和计算机(主机)联系才能实现上述过程。
与智能卡配合使用的接口设备(或称为读写设备、读卡器)应该提供附加的存储器和逻辑电路，它本身可能就是一台微机。
参与智能卡操作的相关方面有：持卡人或用户，商店，卡片的发行者及销售部门，卡片的设计者、出售商及安全维护。
设计目标应满足用户及商店的要求。电子设备应保证能够每天24小时不间断工作，并能很容易测试判断智能卡是否工作正常。机械设计要保证设备和零件工作可靠。设计好对例外情况的处理办法t并能迅速排除故障。
1．2．7智能卡的种类
1．信用卡 卡中预先建立允许透支的限额，即预先设置好可借用的资金额度，承谱到期归还并支讨利息的责仟。根据持卡人信用程度的不同，有两种信用卡：金卡和普j园长。前者的透支限额高。
智能卡的作用是替代流通领域中的现金或支票，随着智能卡的推广使用，利用它进行欺诈或作弊的行为也会不断增加，对于出现的不安全问题的解决办法需要在提供合理的效果和防护的保证与所需的成本和投资之间进行平衡，从而提出一个折衷的解决办法。
在众多智能卡安全问题中有下列基本问题需要解决：
1．3．2安全措施
为了安全防护，一般采取以下措施：
1．3．3密钥与认证
为实现数字签名，一般要求用公共密钥解决。
从磁卡使用情况来看，造成发卡行损失的有两种情况，
1．4识别卡的国际标准
由于信用卡可在国内备地使用，某些还能在国外使用，因此制定国际和国家标准是迫切需要的，国家标准应该尽量与国际标准一致。
1．物理特性 包括卡的材料、构造、特性、标称尺寸等均应符合国际标准ISO7816：1985。
1．4．2 IC卡(接触型)的国际标准
1．物理特性 符合ISO7816：1987中规定的各类识别卡的物理特性和ISO7813中规定的金融交易卡的全部尺寸要求，此外还应符合国际标准ISO7816—1：1987规定的附加特性、机械强度和静电测试方法。
(转自：≡中国电子技术信息网≡ 网址： www.EC66.com)