VerilogHDL二分频代码

VerilogHDL二分频代码

①二分频代码

module FP2(
input clk,
output reg clk_s
);
initial
clk_s <= 1'b0;              //初始化
 always @(posedge clk)      //时钟上升沿敏感
 begin
   if(clk == 1'b1)           //当时钟为高电平
     clk_s <= ~clk_s;        //二分频输出翻转
 end
endmodule

②测试文件代码

`timescale 1ns/1ps
module FP2_TEST;
  reg clk;
  
  initial
  begin
    clk = 0;                 //初始化时钟输入为0
  end
  
  always #20 clk = ~clk;    //设置输入时钟，频率为25Mhz
  
  FP2 U1(
  .clk(clk),
  .clk_s(clk_s)
  );
endmodule

③仿真波形