mit 6.002 circuits & electronics video note

21:48 2013-3-19 星期二
the art of electronics chapter 1 done!

LCA == Lumped Circuit Abstraction

LMD == Lumped Matter Discipline

"I'm going to discipline myself..."

22:36 2013-3-19
6.002(circuits) lec 1 done!

/////////////////////////////////////////
19:12 2013-3-20 星期三

method 1: KVL, KCL

element v-i

KVL for all loops

KCL for all nodes...

19:14 2013-3-20
associated variable discipline

method 2: intuitive method

method 3: node method

  1. select ground node
  2. label node voltage
  3. apply KCL for each node

6.002 has prerequisite: 8.02, 18.03(diff eqs)

LMD playground..

20:04 2013-3-20
2 methods which only apply to "linear circuits"!

superposition

Thevenin

20:26 2013-3-20
??????????????????
superposition for "dependent source"?

20:50 2013-3-20

Thevenin method:

linear network...

1.open circuit voltage

2.short circuit current

use "superposition"!

21:02 2013-3-20
Thevenin equivalent........

21:25 2013-3-20
How to derive Thevenin method?

1. assume linear network

2. abstract with box, apply current source!

3. apply superposition!

21:34 2013-3-20

How to find thevenin resistance?

zero all indepent source(open voltage source, short current source)

then measure the resistance!

this implies "linear"! (apply only the outer current source)

21:37 2013-3-20
Why measure open circuit voltage?

again because linear!

zero outer current(open), measure voltage!

V = Vth + Ri (linear)

21:49 2013-3-20
go digital!

LMD == Lump Matter Discipline

LCA == Lump Circuit Abstraction

22:02 2013-3-20
ASP == Analog Signal Processing

22:05 2013-3-20
"noise is a fact of life!"

"value discretization"

22:07 2013-3-20
Why digitial?

"noise immunity"

"noise margin"

22:17 2013-3-20
How to design "noise margin"?

"no mans land" <-> forbidden region

22:19 2013-3-20
Vh == High threshold

Vl == Low threshold

22:21 2013-3-20
"I'm going to discipline myself to play in this playground!"

22:30 2013-3-20
the real meaning of "noise margin"?

VOH, VOL, VIH, VIL

VIL - VOL,  VOH - VIH

22:34 2013-3-20
NM == Noise margin

22:39 2013-3-20
static discipline

NM reflects tolerance of noise!

22:45 2013-3-20
combinational gate

boolean algebra

TT == truth table

23:00 2013-3-20
6.002 lec4 done!

///////////////////////////////////////////////////////////////
18:56 2013-3-21

static discipline

NAND gate

inverter

mix signal circuit

digital gate -> switch(control, input, output)

????????????????????????????????
20:14 2013-3-21
last see 6.002, 2008, now 2013

NOR

switch -> input, output, control(MOSFET)

20:32 2013-3-21
MOSFET

D, G, S

D == Drain

G == Gate

S == Source

VGS, VDS

IG == 0, iDS

S(Switch) model of the MOSFET

21:05 2013-3-21
digital circuits are essentially nonlinear

but can be linearized by fix the switch settings...

21:08 2013-3-21
LCA == Linear + nonlinear

KVL, KCL, node analysis, composition

Linear:
  superposition, thevenin, norton

Nonlinear:
  ??? can be transformed to linear by fix switch setting...

digital circuits are essentially nonlinar!(just see their nonlinar

transfer function!)

21:11 2013-3-21
then how to analyze nonlinear circuits?

1. analytical

2. graphical

3. piecewise linear model

4. incremental analysis(small signal analysis)

21:32 2013-3-21
suddenly can not recall how to derive Thevenin's law?

//////////////////////////////////////////////////////////////
21:18 2013-3-22
lec5 -> go inside the digital gate

static discipline: analog to digital..

21:25 2013-3-22
NAND gate

21:40 2013-3-22
faucet(tap) as switch,,,,,,,

switch

transistor as a switch...

21:43 2013-3-22
transistor as a 3-terminal switch: control, input, output

21:51 2013-3-22
inverter implemented with a transistor...

22:05 2013-3-22
short <-> open.....

NOR gate....

22:18 2013-3-22
MOSFET

22:23 2013-3-22
Switch model of the MOSFET

also "S model of the MOSFET"

22:25 2013-3-22
just like a faucet!

VGS > VTH, short circuit!

VGS < VTH, open circuit!

22:47 2013-3-22
6.002 lec5 done!

23:17 2013-3-22
nonlinear analysis

because LCA includes both "linear" & "nonlinear"

KVL, KCL, node analysis still hold for nonlinear circuit,

but superposition & Thevenin does not hold for nonlinear circuit..

23:20 2013-3-22
How to analyze nonlinear circuit?

1. analytic

2. graphic

3. piecewise-linear model

4. incremental analysis(small signal)

23:22 2013-3-22
NLD == Non-Linear Device

23:31 2013-3-22
Thevenin Equivalent(or Norton Equivalent)

23:38 2013-3-22
"playground": LCA, linear, nonlinear etc...

23:43 2013-3-22
graphic analysis:

superimpose these 2 curves, and find the intersection!

23:43 2013-3-22
load line

23:45 2013-3-22
piecewise linear technique

23:50 2013-3-22
PR == Photo Resistance

23:52 2013-3-22
incremental analysis(small signal analysis)

23:52 2013-3-22
why incremental?

sender: LED

receiver: PR

distortion?

23:59 2013-3-22
LED is a NLD!  VI, ID

0:04 2013-3-23
input, distorted output

 

 

 

 

 

 

////////////////////////////////////////////
9:37 2013-3-23 星期六
incremental analysis...

9:43 2013-3-23
superimpose AC signal(small signal) + DC offset........

boost & shrink

boost using DC offset

9:47 2013-3-23
bump my signal up & shrink it!

9:52 2013-3-23
key: why incremental analysis(small signal)?

by shrink the signal small, only map to small portion

of the transfer function(transfer curve), thus approximate

linear transfer characteristic!

9:55 2013-3-23
big aha moment!

9:56 2013-3-23
total signal == DC offset + small signal

10:02 2013-3-23
small signal model
1. operate at some DC offset(DC bias)

2. superimpose a small signal

3. observe response....

10:03 2013-3-23
dc offset == dc bias

10:14 2013-3-23
essense of incremental analysis:

Taylor's series expansion

omit all higher order terms: f(x) == f(x0) + slope at x = x0 * delta

tangent line approximation........

10:27 2013-3-23
input excursion & output excursion are linearly related

10:30 2013-3-23
dc bias point...

10:31 2013-3-23
the essense of small signal analysis:

linear approximation....

10:44 2013-3-23
lec 7(incremental analysis) done!
------------------------------------------------------------------------------------------

 

 

10:52 2013-3-23
start lec8: dependent source & amplifier

10:53 2013-3-23
node method:

  when in doubt, using node method, which applies

both to linear & nonlinear circuits...

10:58 2013-3-23
voltage swing

power gain(compare: voltage gain, current gain)!

power port

13:01 2013-3-23
small variation, small regime....(nonlinear -> linear)

13:07 2013-3-23
dependent source & amplifier

13:07 2013-3-23
PP == Power Port

13:14 2013-3-23
LNA == Low Noise Amplifier

13:18 2013-3-23
digital & amplify "to attack noise"

13:19 2013-3-23
analog signal -> amplify -> digitize

13:20 2013-3-23
static discipline

VIH, VIL, VOH, VOL

13:22 2013-3-23
output standard must be stricter than that of input!

13:26 2013-3-23
digital system must has amplification built into it, why?

because: must meet "minimum amplification" == (VOH - VOL) / (VIH - VIL)

13:29 2013-3-23
mixed-signal circuit

13:38 2013-3-23
dependent source: control port, output port

13:41 2013-3-23
VCCS == Voltage Controlled Current Source

CCCS == Current Controlled Current Source

13:47 2013-3-23
CS == Current Source

13:53 2013-3-23
the workhorse of the circuit industry: node analysis

14:15 2013-3-23
see MOSFET as VCCS(Voltage Controlled Current Source),

then we got an amplifier!

because (delta VO / delta VI) > 1

14:26 2013-3-23
the model breaks down..
----------------------------------------------------------------------------------

 

15:19 2013-3-23
start lec9 MOSFET amplifier

dependent source -> amplifier

15:21 2013-3-23
How to deal with "dependent source" when using superposition?

ans: just leave them as it is...

deal with independent source one each time!

15:26 2013-3-23
dependent source amplifier: MOSFET amplifier

dependent source: control port, output port

key: IDS = F(VGS)

15:33 2013-3-23
MOSFET as a VCCS(Voltage Controlled Current Source)

15:34 2013-3-23
3-terminal device

15:39 2013-3-23
when VGS < VT(threshold voltage), the switch is open

15:40 2013-3-23
SR model of the MOSFET: when VGS > VT, view switch as "resistor"

S model of the MOSFET: when VGS > VT, view switch as "short circuit"

15:47 2013-3-23
plot(picture) of MOSFET:

x axis == VDS

y axis == IDS

every VGS determine a single curve, there are many curves(since many different VGS)

15:53 2013-3-23
if VGS > VT, what does happen if VDS continues to grow?

ans: IDS stops grow linearly with VDS, instead, it gradually bends,

approximate some limit, thus shows "current source" behavior.

15:56 2013-3-23
that's what called "saturatation"

SR model breaks down!

15:58 2013-3-23
SCS model of MOSFET

SCS == Switch Current Source, when

1. VGS > VT          // MOSFET is ON

2. VDS >= (VGS - VT) // MOSFET saturates, the regional behavior, just like a "current source"

16:05 2013-3-23
What's the relationship between SR model & SCS model?

if VGS > VT, then MOSFET is ON,

   1. if VDS < (VGS - VT), MOSFET behaves like a "resistance"
       // ramp

   2. else VDS > (VGS -VT), MOSFET behaves like a "current source"
       // horizontal

16:10 2013-3-23
saturation region

triode region

16:13 2013-3-23
resistance like behavior       // VDS < (VDS -VT)

current source like behavior   // VDS > (VGS - VT)

16:18 2013-3-23
When to use SR model & SCS model?

digital design: use SR model
                // Switch Resistance

analog design(amplifier etc): using SCS model
                // Switch Current Source

16:52 2013-3-23
How to analyze MOS AMP?

ans: when use MOSFET as Amplifier, use SCS model(Switch Current Source)

with "saturation discipline", it's easy to solve:

VGS > VT // MOSFET is ON

assume VDS > (VGS - VT), saturation

VGS -> IDS -> VDS

 

16:55 2013-3-23
when deal with MOS AMP, use "current source" model // SCS model

 

-------------------------------------------
16:59 2013-3-23
MOSFET in saturation, if

1. VGS > VT // MOSFET is ON

2. VDS > (VGS - VT) // MOSFET in saturation

then we can use VCCS model for MOSFET,

control port: VGS(VIN)

17:08 2013-3-23
What's a "saturation discipline"?

1. VGS > VT

2. VDS > (VGS - VT)

17:17 2013-3-23
load line

17:18 2013-3-23
operating point

--------------------------------------------------
21:38 2013-3-23
larget signal analysis

BJT == Bipolar Junction Transistor

21:41 2013-3-23
operating points

21:43 2013-3-23
saturation region

21:47 2013-3-23
large signal analysis:

1. VO vs VI

2. find valid input operating range

21:54 2013-3-23
valid operating range

valid input operating range -> valid output operating range

find throught VI, VO relationship

22:19 2013-3-23
transfer function

using saturation constraints to derive "valid operating range"

VI > VT

VO > (VI - VT)  // plot in transfer function(VI <-> VO)

22:22 2013-3-23
bounding point of such regime(operating regime)

22:23 2013-3-23
corresponding output range

22:24 2013-3-23
transfer curve

22:24 2013-3-23
transfer function

22:25 2013-3-23
triode region

22:27 2013-3-23
loadline characteristic

22:29 2013-3-23
loadline graph(VDS <-> IDS)

22:30 2013-3-23
saturation constraint: VGS > VT, VDS > VGS - VT

22:31 2013-3-23
triode region + saturation region

22:32 2013-3-23
loadline equation

22:34 2013-3-23
graph method can intuitively determine the operating range!

using loadline superimposed

22:48 2013-3-23
transfer people vs loadline people

22:57 2013-3-23
boost the signal to go in valid input operating range.....

22:59 2013-3-23
overdrive the input

 

 

//////////////////////////////////////////////////////////////////////////
10:16 2013-3-24 星期天
review lec8
dependent source & amplifier

10:29 2013-3-24
why amplify?

1. amplify signal to get better noise immunity

10:34 2013-3-245
LNA == Low Noise Amplifier

10:39 2013-3-24
amplification is fundamental to the digital domain,

because (VOH - VOL) > (VIH - VIL)

that is the NM(Noise Margin)

10:40 2013-3-24
static discipline:

VIH, VIL, VOL, VOH

10:45 2013-3-24
output requirement is tuffer(stricter) than the input ones!

10:49 2013-3-24
low noise high gain amplifier

10:49 2013-3-24
input stage

10:52 2013-3-24
dependent source: control port, output port

10:54 2013-3-24
VCCS == Voltage Controlled Current Source

10:56 2013-3-24
"output current" is controlled by "input voltage"

10:58 2013-3-24
drop across thr resistor

10:59 2013-3-24
CS == Current Source

independent CS, dependent CS

11:08 2013-3-24
the control port input impedance is infinite,

it does not affect the circuit in anyway...

11:11 2013-3-24
transfer function(transfer characteristic):

VO vs VI

11:13 2013-3-24
RL // Load Resistance

11:21 2013-3-24
if I can find a region of the curve which has delta VO > delta VI,

then it amplifies!

11:25 2013-3-24
linear amplifier + nonlinear amplifier

11:29 2013-3-24
How can you see amplification from the transfer function?

small input variation -> big output variation  // steep transfer behavior

11:31 2013-3-24
transfer characteristic

VO = f(VI)

11:33 2013-3-24
passive device: which can not produce power

11:37 2013-3-24
as VI increases, the device stops behaving like a "dependent source",

and the model breaks down

------------------------------------------------
16:16 2013-3-24
MOSFET amplifier

16:17 2013-3-24
build an amplifier with an independent source

16:18 2013-3-24
terminal pair(port)

16:23 2013-3-24
control port of the dependent source

16:23 2013-3-24
does not draw any current like that....(IG == 0)

16:25 2013-3-24
drop across the resistor

16:32 2013-3-24
threshold voltage VT

16:44 2013-3-24
plot IDS vs VDS........

16:46 2013-3-24
MOSFET model:

1. S model  (Switch)

2. SR model (Switch Resistance) // when VDS is small, triode region

16:51 2013-3-24
How to plot MOSFET behavior?

1. fix some VGS

2. plot IDS <-> VDS

16:52 2013-3-24
What does saturate mean?

if VGS > VT, MOSFET is operating,

normally(triode region) IDS is proportion to VDS,

but when VDS > VGS - VT, IDS stops increasing as VDS increase,

thus MOSFET saturates, it behaves like a "current source"

16:54 2013-3-24
"I give up!" // saturates, VDS is too big, IDS gives up!

16:56 2013-3-24
large signal analysis

16:59 2013-3-24
when saturates, MOSFET behaves like a "current source",

the curve is horizontal // IDS approaches constant, VDS is irrevalent!

17:02 2013-3-24
MOSFET as an amplifier:

1. VGS > VT       // MOSFET IS ON

2. VDS > VGS - VT // MOSFET SATURATES

17:04 2013-3-24
the different between SR MODEL & SCS MODEL?

SR MODEL <-> triode region

SCS MODEL <-> saturation region

17:08 2013-3-24
How does MOSFET operate?

1. if VGS < VT, MOSFET IS OFF

2. else VGS > VT, MOSFET IS ON
  
   2.1 IF VDS < VGS - VT, triode region, SR model, "resistor"

   2.2 ELSE VDS > VGS - VT, saturation region, SCS model, "current source"

17:11 2013-3-24
triode region & saturation region........

17:13 2013-3-24
resistor behavior & current source behavior

17:21 2013-3-24
When to use SR model, SCS model?

1st, it must be met that: 
                          VGS > VT // MOSFET IS ON

1. VDS < VGS - VT, use SR model  // because in triode region

2. VDS > VGS - VT, use SCS model // because in saturation region

17:24 2013-3-24
operating MOSFET in a saturation region......

17:25 2013-3-24
What's the difference between using MOSFET in ANALOG & DIGITAL?

DIGITAL: in triode region, use SR model

ANALOG: use MOSFET as amplifier etc, in saturation region, use SCS model

17:28 2013-3-24
saturation discipline.....

17:29 2013-3-24
primitive inverter circuit

17:30 2013-3-24
generally speaking

triode region: VDS is small

saturation region: VDS is big   // VDS compared with (VGS - VT)

17:31 2013-3-24
for amplication, let's follow the saturaton discipline!

17:33 2013-3-24
linear region == triode region

17:33 2013-3-24
How to analyze MOSFET circuit?

if amplification, use "saturation discipline",

replace MOSFET with "SCS model" // current source

17:35 2013-3-24
current source model applies // SCS model

17:37 2013-3-24
assumes the MOSFET is in saturation!

17:42 2013-3-24
How to analyze MOS AMP?

assume MOSFET operates in saturation region,

then IDS is irrelevant with VDS(because current source behavior),

thus IDS is solely determined by VGS!

then MOSFET can be viewed as "VCCS"!

control port: VGS

output port:  IDS

replace MOSFET with VCCS(Voltage Controlled Current Source)!

MOSFET becomes a "dependent source"!

17:47 2013-3-24
We are operating under the "saturation discipline"!

17:48 2013-3-24
How to deal with "nonlinear circuits"?

1. generally by using KVL, KCL, nodal analysis
                    // these method applies disregard of linearity

2. "analytical method" or "graphical method"  // may be "loadline"?

17:55 2013-3-24
the condition under which it applies is the "saturation discipline"

17:59 2013-3-24
SAT == Saturation

18:00 2013-3-24
What is a graphical analysis method?

plot both linear & nonlinear part of circuit together:

means to superimpose these 2 parts,

then the "intersection" is the "operating point" of the circuit

18:02 2013-3-24
loadline: curve of the linear part of circuit

18:04 2013-3-24
device characteristic // e.g. IDS = f(VDS), VGS...

18:05 2013-3-24
What is a large-signal analysis?

given a device characteristic,

how to figure out the boundary of the valid operation

so that the MOSFET stays in saturation?

18:06 2013-3-24
operating point of the MOSFET  // VDS, IDS, VGS

------------------------------------
boundary of the valid operation
------------------------------------

18:10 2013-3-24
lec9 review done!

 

 

/////////////////////////////////////////////////////////////////
19:27 2013-3-25
large signal analysis:

find the conditions under which MOSFET always work

in saturation.

19:57 2013-3-25
1. plot transfer graph

2. using saturation discipline to find proper region:

  VGS > VT, VDS > VGS - VT

3. got input operating range, output operating range

saturation can always be ensured in this operating range

20:14 2013-3-25
Can you see "cutoff region", "saturation region", "triode region"

from transfer graph?

------------------------------------------------------------
20:44 2013-3-25
lec10 amplifier: small signal analysis

20:51 2013-3-25
saturation discipline

20:53 2013-3-25
the main reason why "large signal analysis"?

find the operating range under which the "saturation discipline"

holds.....

20:57 2013-3-25
Why small-signal analysis?

because the saturation region of the transfer function is not perfect linear,

just see the transfer graph(saturation region) of MOSFET amplifier!

you got a nonlinear amplifier!

but actually you want a linear amplifier!

solution: small signal

21:07 2013-3-25
operating point: VI, VO, IDS

21:17 2013-3-25
DC bias point

21:17 2013-3-25
large signal response // nonlinear

small signal response // linear

21:21 2013-3-25
How to use a small signal?

1. determine proper "operating point" // DC bias point

2. shrink the signal & boost it!

21:25 2013-3-25
bias point == operating point

21:34 2013-3-25
total variable = DC bias(operating voltage) + small signal input(incremental input)

21:37 2013-3-25
We'are engineers, let's see how we can simplify our lives!

21:41 2013-3-25

vi << VI // small signal

 

21:50 2013-3-25
operating point

21:53 2013-3-25
ss == small signal

21:56 2013-3-25
the essense of small signal analysis:

linear approximation at operating point

21:59 2013-3-25
How to choose the bias point?

1. gain  // proportional to VI, RL

2. distortion range

3. valid input range

-------------------------------------------
22:17 2013-3-25
find slope of the function at the operating point....

22:21 2013-3-25
total variable == DC bias + small signal

22:21 2013-3-25
output vs input relationship // transfer function

22:23 2013-3-25
assume vi << VI, then omit vi * vi,

got vo == A * vi // linear relationship

22:25 2013-3-25
superimpose a loadline on the device characteristic!

graphical analysis

22:26 2013-3-25
Why solve the intersection of loadline & device characteristic?

think it as we solve "system of equation",

both equation must be satisfied

22:27 2013-3-25
What does the intersection mean?

operating point: VI(VGS), VO(VDS), IDS

22:31 2013-3-25
How do we choose bias point?

1. gain             // VI increase -> gain increase

2. input swing range

22:49 2013-3-25
increase bias voltage -> increase gain

22:57 2013-3-25
small signal equivalent

large signal equivalent

22:58 2013-3-25
just replace LS model with SS model, then from nonlinear circuit

we got linear circuit!

23:00 2013-3-25
input loop, output loop

KVL of input loop

KVL of output loop

KCL of IDS etc.........

23:02 2013-3-25
quiescent point

23:07 2013-3-25
small signal circuit model

1. find bias point using LS model

2. develop SS model of my element..

3. replace

23:09 2013-3-25
LS model of MOSFET

23:10 2013-3-25
How to find SS model from LS model?

y = f(x), just find

delta y = ff(delta x) // SS model

23:13 2013-3-25
the SS model of MOSFET is linear VCCS

the LS model of MOSFET is nonlinear VCCS

23:14 2013-3-25
ids = Gm * vgs  // Gm transconductance

23:29 2013-3-25
lec11 done!

///////////////////////////////////////////////////////////////
21:07 2013-3-26 星期二

22:03 2013-3-26
lec13, capacitors & first-order circuits

22:52 2013-3-26
paticular solution

homogeneous solution

constant

23:16 2013-3-26
lec13 Digital circuit speed.

/////////////////////////////////////////////////
20:08 2013-3-27 星期三
lec13 Digital Circuit Speed......

RC dealy

Cgs.........

20:27 2013-3-27
rising delay....

20:42 2013-3-27
falling decay

20:56 2013-3-27
just do the RC

20:56 2013-3-27
Tr == rising time

 proportional to Rl * Cgs

Tf == falling time

21:00 2013-3-27
If I decrease RL, then got sharp rising?

but disaster may happen!

close pin may form capacitor!

this is called "crosstalk"

slower may be better!

21:07 2013-3-27
state & memory lec14

DRAM == Dynamic Random Access Memory

21:22 2013-3-27
ZIR == Zero Input Response

ZSR == Zero State Response

21:34 2013-3-27
total response == ZIR + ZSR

21:34 2013-3-27
combination logic + memory

22:08 2013-3-27
SRAM == Static RAM

////////////////////////////////////////////////
19:29 2013-3-28 星期四
state & memory

20:05 2013-3-28
basic memory element

20:08 2013-3-28
store(charge), discharge

20:09 2013-3-28
discharge == decaying exponential

charge == growing exponential.......

20:29 2013-3-28
2nd order system.......

//////////////////////////////////////////////////////
22:49 2013-3-29 星期五
back from internet bar.....

2nd order system

///////////////////////////////////////////////////////////
8:25 2013-3-30 星期六
start lec15

13:36 2013-3-30 星期天
SSS == Sinusoidal Steady State

15:22 2013-3-30
lec18 filters

15:42 2013-3-30
LPF == Low Pass Filters

///////////////////////////////////////////////////
12:02 2013-3-31 星期天
lec19 op-amp, feedback done!

19:38 2013-3-31
lec21 op-amp positive feedback done!

20:06 2013-3-31
op-amp as VCVS(Voltage Controlled Voltage Source)

20:07 2013-3-31
inverting terminal(negative feedback)

non-inverting terminal(positive feedback)

20:10 2013-3-31
static view of the circuit.......

20:14 2013-3-31
dynamics of op-amp........

20:18 2013-3-31
when deal with positive feedback op-amp,

use the dynamic model with 2 dependent source......

20:20 2013-3-31
perturb the output a little bit.......(some noise)

20:42 2013-3-31
basic comparator(open loop)

20:43 2013-3-31
transfer characteristic........

20:46 2013-3-31
the fault of basic comparator: ringing effect........

20:49 2013-3-31
comparator using positive feedback(Schemitter characteristic)

21:03 2013-3-31
hysteresis

21:07 2013-3-31
lec21 op-amp positive feedback review done!

//////////////////////////////////////////////////////////
19:23 2013-4-1 星期一
lec22 energy & power

19:29 2013-4-1
clock provides the notion of time to the circuit!

19:36 2013-4-1
power dissipation

19:40 2013-4-1
standby power

active use power

19:45 2013-4-1
supply, dissipite

19:50 2013-4-1
power comsumption

19:55 2013-4-1
drive a MOSFET inverter with a square wave

19:58 2013-4-1
energy supplied by the source
 
  == some dissipiated on resistor + some stored in capacitor.......

20:14 2013-4-1
charging & discharging capacitors..

20:14 2013-4-1
switching capacitors..

20:15 2013-4-1
average power of sth ==

C * Vs * Vs * f      // f is frequency of the square wave

in order to decrease power -> decrease power supply voltage(Vs), decrease switching speed(f)

20:21 2013-4-1
standby power == consumed by load resistor

dynamic power == charging & discharing

 

20:34 2013-4-1
start lec23, Energy, CMOS

20:36 2013-4-1
static power(standby power)

dynamic power

20:49 2013-4-1
CMOS == Complementary MOS

20:51 2013-4-1
N-Channel MOSFET == NFET

P-Channel MOSFET == PFET

20:54 2013-4-1
the difference:

when VGS > VTN, NFET is ON,

when VGS < VTP, PFET is ON

20:56 2013-4-1
instead of the resistor, I put a complementary device......

20:57 2013-4-1
PU == Pull Up

PD == Pull Down

21:03 2013-4-1
CMOS logic

CMOS == PMOS + NMOS

21:04 2013-4-1
CMOS is a superior inverter, which consumes less power.......

21:08 2013-4-1
What's the virtre of CMOS compared with NMOS?

1. cuts off static power(standby power)

2. significantly faster because Ron << RL, charging is faster!

21:11 2013-4-1
equivalent circuit of CMOS

T1: charging

T2: discharging

21:12 2013-4-1
static power(standby power) is completely removed!

21:17 2013-4-1
the power of CMOS:

   C * Vs * Vs * f

21:19 2013-4-1
increase f, get faster microprocessor!

decrease Vs, get smaller power.....

21:36 2013-4-1
start lec25(lec24 no available)

violating the abstraction barrier......

21:39 2013-4-1
LMD == Lumped Matter Discipline

LCA == Lumped Circuit Abstraction

21:47 2013-4-1
the 6.002 playground

21:52 2013-4-1
propagation time of the signal

coaxial wire.....

21:54 2013-4-1
capacitance & inductance of wire..

21:55 2013-4-1
transmission line effect

21:57 2013-4-1
LMD applies when the circuit speed is

much slower than the speed of light......

22:00 2013-4-1
hit the other end, reverse, and come back to me....

22:03 2013-4-1
the return wave

22:05 2013-4-1
the standard lumped model

22:06 2013-4-1
the end of the cable........

22:07 2013-4-1
put the resistor at the end.....

22:07 2013-4-1
put the resistor at the end to absorb energy

22:08 2013-4-1
characteristic impedance.....

22:09 2013-4-1
line terminator

22:13 2013-4-1
transmission line effect, solution:

1. line terminator(resistor etc.)

2. use short cable instead......

3. use a clock (to sample at a later time)

22:18 2013-4-1
case 2: Double DIP

22:21 2013-4-1
dip(opposite of spikes)

22:22 2013-4-1
CMOS inverter

22:23 2013-4-1
the dips & spikes on the inverter output....

22:27 2013-4-1
really long wire

22:30 2013-4-1
inductance effect of the long wire........

22:32 2013-4-1
the higher the speed of the circuit,

 the smaller the circuit must be(short wire)

22:34 2013-4-1
each leaf of the tree draw some current.

22:35 2013-4-1
power supply buffering tree.........

22:37 2013-4-1
sharp edges -> smoother edges, then you have small di/dt

22:39 2013-4-1
capacitor coupling between adjacent pins of the IC

22:40 2013-4-1
solution: sharp transition -> smoother transition

22:40 2013-4-1
faster transition is nasty!

22:40 2013-4-1
THE END OF 6.002!