vivado问题记录 [Place 30-132] Unroutable Placement! A BUFR / MMCM component pair is not placed

[Place 30-132] Unroutable Placement! A BUFR / MMCM component pair is not placed in a routable site pair. The pair can use the dedicated path between them if they are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets DAQ_i/adc_interface_ch2_0/inst/dclk/CLK] >

    DAQ_i/adc_interface_ch2_0/inst/dclk/BUFR_dclk (BUFR.O) is locked to BUFR_X0Y18
     dbg_hub/inst/BSCANID.u_xsdbm_id/USE_DIVIDER.N_ULTRASCALE.U_GT_MMCM (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y3

    The above error could possibly be related to other connected instances. Following is a list of 
    all the related clock rules and their respective instances.

。。。。。

vivado2019.1

解决办法::实现时不要选择增量布局，在clk输出要驱动其他模块时一定要加bufG