FPGA学习笔记10--7人表决器

module seven(
input [6:0]vote,
output reg pass
);
reg [2:0]sum;
integer i;
always @(*)begin
	sum=3'b0;
	for(i=0;i<=6;i=i+1)begin
		if(vote[i])
		sum=sum+1'b1;
	end
	if(sum[2])pass=1;
	else pass=0;
end			

endmodule

`timescale 1ns/1ns
module tb_seven();
reg [6:0]vote;
wire pass;
seven vt(.pass(pass),.vote(vote));
initial begin
vote=7'b1110001;
#50 vote=7'b1100000;
#50 vote=7'b1101101;	
#50 $finish;
end

endmodule