VHDL中间信号的使用
在模块化程序设计中，系统模块包括模块A、模块B等等。当你想要将模块A中某一信号的输出当做整个系统模块输出，但这一信号同时又是模块B的输入时，方法是在系统模块中加入一个中间信号变量。例如模块A的输出信号为yi，只需在系统模块中声明一个信号如di，将yi的值赋给di，最后把di作为系统输出，yi作为模块B的输入即可。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity costas is
port(
rst : in STD_LOGIC; --复位信号，高电平有效
clk : in STD_LOGIC; --时钟信号，数据速率/采样速率/FPGA系统时钟/8MHz
din : in STD_LOGIC_VECTOR (7 downto 0); --输入的DPSK已调数据
di : out STD_LOGIC_VECTOR (25 downto 0); --解调后正交支路基带波形
dq : out STD_LOGIC_VECTOR (25 downto 0); --解调后同相支路基带波形
df : out STD_LOGIC_VECTOR (25 downto 0)); --环路滤波器输出频差信号
end costas;
architecture Behavioral of costas is
-----------------------------------------------------------------------------
-- declaration
-----------------------------------------------------------------------------
component fir_lpf
port (
clk : in std_logic;
nd : in std_logic;
din : in std_logic_vector(14 downto 0);
rfd : out std_logic;
rdy : out std_logic;
dout : out std_logic_vector(25 downto 0)
);
end component;
COMPONENT mult8_8
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT;
COMPONENT nco
PORT (
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(29 DOWNTO 0);
cosine : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sine : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT loop_filter
PORT(
clk : IN std_logic;
rst : IN std_logic;
pd : IN std_logic_vector(25 downto 0);
newf_ce : OUT std_logic;
df : OUT std_logic_vector(25 downto 0);
frequency : OUT std_logic_vector(29 downto 0)
);
END COMPONENT;
COMPONENT phase_detect
PORT(
clk : IN std_logic;
yi : IN std_logic_vector(25 downto 0);
yq : IN std_logic_vector(25 downto 0);
pd : OUT std_logic_vector(25 downto 0)
);
END COMPONENT;
-----------------------------------------------------------------------------
-- signal
-----------------------------------------------------------------------------
signal newf_ce : std_logic;
signal frequency : std_logic_vector(29 downto 0);
signal sine,cosine : std_logic_vector(7 downto 0);
signal zi,zq : std_logic_vector(14 downto 0);
signal nd : std_logic;
signal rfdi,rfdq : std_logic;
signal rdyi,rdyq : std_logic;
signal yi,yq : std_logic_vector(25 downto 0);
signal pd : std_logic_vector(25 downto 0);
begin
-----------------------------------------------------------------------------
-- instantiation
-----------------------------------------------------------------------------
nco_inst: nco
port map(
clk => clk,
we => newf_ce,
data => frequency,
cosine => cosine,
sine => sine
);
mult8_8_inst_i: mult8_8
port map(
clk => clk,
a => sine,
b => din,
p => zi
);
mult8_8_inst_q: mult8_8
port map(
clk => clk,
a => cosine,
b => din,
p => zq
);
fir_lpf_i: fir_lpf
port map(
clk => clk,
nd => nd,
din => zi,
rfd => rfdi,
rdy => rdyi,
dout => yi
);
fir_lpf_q: fir_lpf
port map(
clk => clk,
nd => nd,
din => zq,
rfd => rfdq,
rdy => rdyq,
dout => yq
);
loop_filter_inst: loop_filter
port map(
clk => clk,
rst => rst,
pd => pd,
newf_ce => newf_ce,
df => df,
frequency => frequency
);
phase_detect_inst: phase_detect
PORT MAP(
clk => clk,
yi => yi,
yq => yq,
pd => pd
);
di <= yi;
dq <= yq;
nd <= not rst;
end Behavioral;