FPGA学习笔记6--fork-join和begin-end

 `timescale 10ns/1ns 

module wave2; 

reg wave; 

parameter cycle=5; 

initial 

  fork 

                   wave=0; 

     #(cycle)      wave=1; 

     #(2*cycle)  wave=0; 

     #(3*cycle)  wave=1; 

     #(4*cycle)  wave=0; 

     #(5*cycle)  wave=1; 

     #(6*cycle)    $finish; 

  join 

initial $monitor($time,,,"wave=%b",wave); 

endmodule 

语句同时执行

     `timescale 10ns/1ns 
module wave1();
reg wave;
parameter cycle=10;
initial begin
   wave=0; 

   #(cycle/2)  wave=1; 

   #(cycle/2)  wave=0; 

   #(cycle/2)  wave=1; 

   #(cycle/2)  wave=0; 

   #(cycle/2)  wave=1; 

   #(cycle/2)  $finish ; 


end
endmodule

语句按顺序执行