利用VHDL实现VGA的时序。
代码如下:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga_ctr is
port(
clk : in std_logic; --系统时钟输入
hsync : out std_logic;--输出行同步、列同步以及R.G.B信号.其中R.G.G信号位数根据自己开发板的情况修改
vsync : out std_logic;
rvb_in: in Bit_Vector(11 downto 0);
rvb_out: out Bit_Vector(11 downto 0);
pixel_counterx:out std_logic_vector(9 downto 0);
pixel_countery:out std_logic_vector(9 downto 0)
);
end vga_ctr;
architecture behave of vga_ctr is
-- horizontal timing signals
constant h_data: integer:=640; --VGA时序中几个关键数据,具体数据根据自身显示屏情况修改
constant h_front: integer:=16;
constant h_back: integer:=48;
constant h_sync: integer:=96;
constant h_period: integer:= h_sync + h_data + h_front + h_back; --800
-- vertical timing signals
constant v_data: integer:=480;
constant v_front: integer:=10;
constant v_back: integer:=33;
constant v_sync: integer:=2;
constant v_period: integer:= v_sync + v_data + v_front + v_back; --525
signal henable, venable : std_logic;
signal clk25M : std_logic;
signal hcnt: std_logic_vector(9 downto 0); -- horizontal pixel counter
signal vcnt: std_logic_vector(9 downto 0); -- vertical line counter
begin
process(clk)
begin
if (clk'event and clk = '1') then --由系统时钟二分频得到25MHZ的频率信号
clk25M <= not clk25M;
end if;
end process;
process(clk25M) ---行扫描
begin
if (clk25M'event and clk25M = '1') then
if hcnt < h_period then
hcnt <= hcnt + 1;
pixel_counterx<=hcnt;
else
hcnt <= (others => '0');
end if;
end if;
end process;
process(clk25M) --行同步
begin
if (clk25M'event and clk25M = '1') then
if (hcnt >= (h_data + h_front)
and hcnt < (h_data + h_sync + h_front)) then
hsync <= '0';
else
hsync <= '1';
end if;
end if;
end process;
process(clk25M) --列扫描
begin
if (clk25M'event and clk25M = '1') then
if hcnt = (h_data + h_sync + h_front) then
if vcnt < v_period then
vcnt <= vcnt + 1;
pixel_countery<=vcnt;
else
vcnt <= (others => '0');
end if;
end if;
end if;
end process;
process(clk25M) --列同步
begin
if (clk25M'event and clk25M = '1') then
if (vcnt >= (v_data + v_front)
and vcnt < (v_data + v_sync + v_front)) then
vsync <= '0';
else
vsync <= '1';
end if;
end if;
end process;
process(clk25M) --行显示
begin
if (clk25M'event and clk25M = '1') then
if hcnt < h_data then
henable <= '1';
else
henable <= '0';
end if;
end if;
end process;
process(clk25M) --列显示
begin
if (clk25M'event and clk25M = '1') then
if vcnt < v_data then
venable <= '1';
else
venable <= '0';
end if;
end if;
end process;
process(clk25M,henable,venable)
begin
if (clk25M'event and clk25M = '1') then
if(henable='1' and venable='1') then
rvb_out<=rvb_in;
else
rvb_out<="000000000000"; --输出特定数据,观察屏幕能否正常输出颜色
end if;
end if;
end process;
end behave;