Internet interrupt

Interrupt PacingThe receive and transmit pulse interrupts can be paced. The receive threshold and miscellaneousinterrupts are not paced. The Interrupt pacing feature limits the number of interrupts that occur during agiven period of time. For heavily loaded systems in which interrupts can occur at a very high rate (e.g.148,800 packets per second for Ethernet), theInterrupt Pacing
The receive and transmit pulse interrupts can be paced. The receive threshold and miscellaneous
interrupts are not paced. The Interrupt pacing feature limits the number of interrupts that occur during a
given period of time. For heavily loaded systems in which interrupts can occur at a very high rate (e.g.
148,800 packets per second for Ethernet), the performance benefit is significant due to minimizing the
overhead associated with servicing each interrupt. Interrupt pacing increases the CPU cache hit ratio by
minimizing the number of times that large interrupt service routines are moved to and from the CPU
instruction cache.
Each CPU receive and transmit pulse interrupt contains an interrupt pacing sub-block (six total). Each
sub-block is disabled by default allowing the selected interrupt inputs to pass through unaffected. The
interrupt pacing module counts the number of interrupts that occur over a 1ms interval of time. At the end
of each 1ms interval, the current number of interrupts is compared with a target number of interrupts
(specified by the associated maximum number of interrupts register).
Based on the results of the comparison, the length of time during which interrupts are blocked is
dynamically adjusted. The 1ms interval is derived from a 4us pulse that is created from a prescale counter
whose value is set in the int_prescale value in the Int_Control register. The int_prescale value should be
written with the number of VBUSP_CLK periods in 4us. The pacing timer determines the interval during
which interrupts are blocked and decrements every 4us. It is reloaded each time a zero count is reached.
The value loaded into the pacing timer is calculated by hardware every 1ms according to the following
algorithm:
if (intr_count > 2*intr_max)
pace_timer = 255;
else if (intr_count > 1.5*intr_max)
pace_timer = last_pace_timer*2 + 1;
else if (intr_count > 1.0*intr_max)
pace_timer = last_pace_timer + 1;
else if (intr_count > 0.5*intr_max)
pace_timer = last_pace_timer - 1;
else if (intr_count != 0)
pace_timer = last_pace_timer/2;
else
pace_timer = 0;
If the rate of interrupt inputs is much less than the target interrupt rate specified in the associated
maximum interrupts register, then the interrupt is not blocked. If the interrupt rate is greater than the target
rate, the interrupt will be “paced” at the rate specified in the interrupt maximum register. The interrupt
maximum register should be written with a value between 2 and 63 inclusive indicating the target number
of interrupts per milli-second. performance benefit is significant due to minimizing theoverhead associated with servicing each interrupt. Interrupt pacing increases the CPU cache hit ratio byminimizing the number of times that large interrupt service routines are moved to and from the CPUinstruction cache.Each CPU receive and transmit pulse interrupt contains an interrupt pacing sub-block (six total). Eachsub-block is disabled by default allowing the selected interrupt inputs to pass through unaffected. Theinterrupt pacing module counts the number of interrupts that occur over a 1ms interval of time. At the endof each 1ms interval, the current number of interrupts is compared with a target number of interrupts(specified by the associated maximum number of interrupts register).Based on the results of the comparison, the length of time during which interrupts are blocked isdynamically adjusted. The 1ms interval is derived from a 4us pulse that is created from a prescale counterwhose value is set in the int_prescale value in the Int_Control register. The int_prescale value should bewritten with the number of VBUSP_CLK periods in 4us. The pacing timer determines the interval duringwhich interrupts are blocked and decrements every 4us. It is reloaded each time a zero count is reached.The value loaded into the pacing timer is calculated by hardware every 1ms according to the followingalgorithm:if (intr_count > 2*intr_max)pace_timer = 255;else if (intr_count > 1.5*intr_max)pace_timer = last_pace_timer*2 + 1;else if (intr_count > 1.0*intr_max)pace_timer = last_pace_timer + 1;else if (intr_count > 0.5*intr_max)pace_timer = last_pace_timer - 1;else if (intr_count != 0)pace_timer = last_pace_timer/2;elsepace_timer = 0;If the rate of interrupt inputs is much less than the target interrupt rate specified in the associatedmaximum interrupts register, then the interrupt is not blocked. If the interrupt rate is greater than the targetrate, the interrupt will be “paced” at the rate specified in the interrupt maximum register. The interruptmaximum register should be written with a value between 2 and 63 inclusive indicating the target numberof interrupts per milli-second.