ISE verilog 错误及解决记录（不定期更新）

verilog小白，故常常有各种ERROR和WARNING。记录一下平时自己遇到的问题，希望有用。。。

REEOR1：

Unexpected EOF.

翻译：意外的文件结束。

原因：module和endmodule没有匹配。（有时候网上复制下来的代码常常会出现这样的问题）

REEOR2：

Port connections cannot be mixed ordered and named

翻译：端口连接不能混合命令和命名

example ：

Myclock1 c2(
.clk(clk),
.clk1(clk2),
);

原因：调用module的时候最后一个端口后面多了一个逗号。。。好吧，是一个很傻的错误。再次证明了我是初学者。。。

ERROR3:

A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component is placed at site . The corresponding BUFG
   component is placed at site . There is only a
   select set of IOBs that can use the fast path to the Clocker buffer, and they
   are not being used. You may want to analyze why this problem exists and
   correct it. If this sub optimal condition is acceptable for this design, you
   may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this
   message to a WARNING and allow your design to continue. However, the use of
   this override is highly discouraged as it may lead to very poor timing
   results. It is recommended that this error condition be corrected in the
   design. A list of all the COMP.PINs used in this clock placement rule is
   listed below. These examples can be used directly in the .ucf file to
ide this clock rule.
   < NET "OE" CLOCK_DEDICATED_ROUTE = FALSE; >

原因：将组合逻辑电路的值作为了时钟信号（比如always的敏感变量是组合逻辑电路的值），一般是加入.ucf文件之后出现的问题，解决方法是将NET "OE" CLOCK_DEDICATED_ROUTE = FALSE;这一段语句加入.ucf文件中去。但是即使这样做，还是会有一个warning，因为组合逻辑电路信号会因为开关抖动之类的原因产生毛刺，造成always的错误判断。verilog 不建议这种写法，可以考虑将敏感变量设为自带的时钟信号，在always块内部使用组合逻辑电路的值