A Primer on Memory Consistency and Cache Coherence

A Primer on Memory Consistency and Cache Coherence 前三章阅读笔记

1. Memory consistency

   ​ For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory.

   ​ 对于一个共享存储的计算机，存储的一致性模型定义了该计算机的存储系统的结构上可见的行为。一致性的定义为Loads和Stores提供了一些规则，以规定他们如何在主存上执行。

2. Cache coherence

   ​ As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date.

   ​ Cache一致性是存储一致性的一个部分，许多机器会提供cache一致性协议，以保证同一个数据的多个在cache中的副本能够保持最新的状态。

3. Unlike consistency, coherence (or cache coherence) is neither visible to software nor required. Coherence seeks to make the caches of a shared-memory system as functionally invisible as the caches in a single-core system.

   ​ 不像存储一致性，cache的一致性对软件不可见，同时无需可见。Cache的一致性希望使得共享存储系统的多个caches能够在功能上依旧保持不可见的状态（程序员不知道cache的存在），就像单核系统中的cache一样。

4. We define coherence using the single-writer–multiple-reader (SWMR) invariant. SWMR requires that, at any given time, a memory location is either cached for writing (and reading) at one cache or cached only for reading at zero to many caches.

   我们使用SWMR不变量（同一时间只有同一个写或者是多个读存在）来定义cache的一致性。SWMR要求在给定的时间内，一个memory中地址，要不在一个cache中被写，要不在任意个cache中被读。

5. Consistency models define correct shared memory behavior in terms of loads and stores (memory reads and writes), without reference to caches or coherence.

   ​ 存储一致性模型定义了正确的在共享内存上的Loads和Stores的行为，并且和cache或者是cache一致性没有相关关系。

6. A consistency model defines whether this behavior is correct (and thus whether a user must take other action to achieve the desired outcome) or incorrect (in which case the system must preclude these reordering ).

   ​ 存储一致性模型定义了当前行为是对的（因此用户是否必须采取其他行动来实现期望的结果）或者是错的（在这种情况下，系统必须排除这些Reordering）。

7. For a multithreaded program executing with specific input data, the memory model specifies what values dynamic loads may return and what possible final states of the memory are.

   ​ 对于一个有具体的输入数据的多线程程序，存储一致性模型指定了动态执行过程中load会获取到什么数据和最终执行结束后主存的状态。

8. The possibility of incoherence arises only because of one fundamental issue: there exist multiple actors with access to caches and memory. In modern systems, these actors are processor cores, DMA engines, and external devices that can read and/or write to caches and memory.

   ​ 出现不连贯的可能性只是因为一个基本问题：存在多个可以访问缓存和内存的参与者。 在现代系统中，这些参与者是处理器，DMA和可以读取和/或写入高速缓存和存储器的外设。

9. A definition of coherence that is analogous to the definition of SC is that a coherent system must appear to execute all threads’ loads and stores to a single memory location in a total order that respects the program order of each thread. This definition highlights an important distinction between coherence and consistency: coherence is specified on a per-memory location basis, whereas consistency is specified with respect to all memory locations.

   ​ 类似于SC（Sequence Consistency Model）的定义，Cache一致性也有一个定义：一个具有cache一致性的系统必须保证所有线程的针对于同一个主存地址的Loads和Stores的所有顺序必须满足这些Stores和Loads在其原本的线程内部的程序顺序。

   ​ 这个定义突出了Cache一致性和存储一致性的一个重要的不同点：在每一个内存地址的基础上考虑cache一致性，在所有的内存地址上考虑存储一致性。

10. SC is important because it is what many programmers expect of shared memory and provides a foundation for understanding the more relaxed (weak) memory consistency models presented in the next two chapters.

    ​ SC模型非常重要，应为SC是许多程序员希望共享存储系统所期望的存储操作的执行顺序。同时SC为更好的理解更松散的存储一致性提供了基础。

11. A memory consistency model, or, more simply, a memory model, is a specification of the allowed behavior of multithreaded programs executing with shared memory. For a multithreaded program executing with specific input data, it specifies what values dynamic loads may return and what the final state of memory is.

    ​ 一个存储一致性模型或者是存储模型是一组规定，用于指示在多线程的共享存储系统中什么样的存储行为是允许的。对于有具体的输入数据的多线程程序而言，存储模型指定了动态执行中的load能够获取什么值和最终的主存状态。

12. Memory Order：存储器（memory/cache）执行所有处理器发出的Loads和Stores的顺序

    Program Order：处理器在执行程序过程中发出的Loads和Stores之间的顺序

13. An SC execution requires :

    • All cores insert their loads and stores into the memory order respecting their program order,
      regardless of whether they are to the same or different addresses (i.e., a=b or a≠b).

      所有的核将自己的Loads和Stores插入到Memory Order中，但是必须遵从自己的程序顺序，不管这些Loads和Stores是不是同一个地址。

    • Every load gets its value from the last store before it (in global memory order) to the same
      address。

      每个load必须能够获取到在此之前Memory Order中，最后一个针对于同一个地址的Store的结果。​