解决GD睡眠不唤醒的问题

#if 0
void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
{
    /* clear stbmod and ldolp bits */
    PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
    
    /* set ldolp bit according to pmu_ldo */
    PMU_CTL |= ldo;
    
    /* set sleepdeep bit of Cortex-M4 system control register */
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
    
    /* select WFI or WFE command to enter deepsleep mode */
    if(WFI_CMD == deepsleepmodecmd){
        __WFI();
    }else{
        __SEV();
        __WFE();
        __WFE();
    }
    /* reset sleepdeep bit of Cortex-M4 system control register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
}
#endif
void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
{
        static uint32_t reg_snap[ 4 ];
    /* clear stbmod and ldolp bits */
    PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
    
    /* set ldolp bit according to pmu_ldo */
    PMU_CTL |= ldo;

    /* set sleepdeep bit of Cortex-M4 system control register */
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

    reg_snap[ 0 ] = REG32( 0xE000E010 );
    reg_snap[ 1 ] = REG32( 0xE000E100 );
    reg_snap[ 2 ] = REG32( 0xE000E104 );
    reg_snap[ 3 ] = REG32( 0xE000E108 );
    REG32( 0xE000E010 ) &= 0x00010004;
    REG32( 0xE000E180 ) = 0XFF7FF83D;
    REG32( 0xE000E184 ) = 0XBFFFF8FF;
    REG32( 0xE000E188 ) = 0xFFFFFFFF;

    /* select WFI or WFE command to enter deepsleep mode */
    if(WFI_CMD == deepsleepmodecmd){
    __WFI();
    }else{
    __SEV();
    __WFE();
    __WFE();
    }

    REG32( 0xE000E010 ) = reg_snap[ 0 ] ;
    REG32( 0xE000E100 ) = reg_snap[ 1 ] ;
    REG32( 0xE000E104 ) = reg_snap[ 2 ] ;
    REG32( 0xE000E108 ) = reg_snap[ 3 ] ;

    /* reset sleepdeep bit of Cortex-M4 system control register */
    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
}

#if 0
void SystemSelectPLL(void)
{
    uint32_t timeout = 0U;
    uint32_t stab_flag = 0U;

    if (RCU_CTL & RCU_CTL_HXTALEN) return;
    /* enable HXTAL */
    RCU_CTL |= RCU_CTL_HXTALEN;

    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
    do{
        timeout++;
        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));

    /* if fail */
    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
    {
        GTK_LOG_ERR(GTK_DBG_DRV_RTC, "RTC error %s", __func__);
        while(1)
        {
        }
    }

    /* enable PLL */
    RCU_CTL |= RCU_CTL_PLLEN;

    /* wait until PLL is stable */
    while(0U == (RCU_CTL & RCU_CTL_PLLSTB))
    {
    }

    /* enable the high-drive to extend the clock frequency to 48 MHz */
    PMU_CTL |= PMU_CTL_HDEN;
    while(0U == (PMU_CS & PMU_CS_HDRF)){
    }

    /* select the high-drive mode */
    PMU_CTL |= PMU_CTL_HDS;
    while(0U == (PMU_CS & PMU_CS_HDSRF)){
    }

    /* select PLL as system clock */
    RCU_CFG0 &= ~RCU_CFG0_SCS;
    RCU_CFG0 |= RCU_CKSYSSRC_PLL;

    /* wait until PLL is selected as system clock */
    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
    }
}
#endif


void SystemSelectPLL(void)
{
    uint32_t timeout = 0U;
    uint32_t stab_flag = 0U;

    if (RCU_CTL & RCU_CTL_HXTALEN) return;
    /* enable HXTAL */
    RCU_CTL |= RCU_CTL_HXTALEN;

    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
    do{
        timeout++;
        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));

    timeout = 0;
    /* if fail */
    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
    {
//        GTK_LOG_ERR(GTK_DBG_DRV_RTC, "RTC error %s", __func__);
        while(1)
        {
            timeout++;
            if (timeout > HXTAL_STARTUP_TIMEOUT)
            {
//                GTK_LOG_ASSERT(GTK_DBG_DRV_RTC, "RTC error %d", __LINE__);
//                GTK_ASSERT(0);
            }
            timeout = 0;
        }
    }

    RCU_APB1EN |= RCU_APB1EN_PMUEN; //10.12
    PMU_CTL |= PMU_CTL_LDOVS; //10.12

    /* enable PLL */
    RCU_CTL |= RCU_CTL_PLLEN;

    /* wait until PLL is stable */
    while(0U == (RCU_CTL & RCU_CTL_PLLSTB))
    {
        timeout++;
        if (timeout > HXTAL_STARTUP_TIMEOUT)
        {
//            GTK_LOG_ASSERT(GTK_DBG_DRV_RTC, "RTC error %d", __LINE__);
//            GTK_ASSERT(0);
        }
        timeout = 0;
    }

    /* enable the high-drive to extend the clock frequency to 48 MHz */
    PMU_CTL |= PMU_CTL_HDEN;
    while(0U == (PMU_CS & PMU_CS_HDRF)){
        timeout++;
        if (timeout > HXTAL_STARTUP_TIMEOUT)
        {
//            GTK_LOG_ASSERT(GTK_DBG_DRV_RTC, "RTC error %d", __LINE__);
//            GTK_ASSERT(0);
        }
        timeout = 0;
    }

    /* select the high-drive mode */
    PMU_CTL |= PMU_CTL_HDS;
    while(0U == (PMU_CS & PMU_CS_HDSRF)){
        timeout++;
        if (timeout > HXTAL_STARTUP_TIMEOUT)
        {
//            GTK_LOG_ASSERT(GTK_DBG_DRV_RTC, "RTC error %d", __LINE__);
//            GTK_ASSERT(0);
        }
        timeout = 0;
    }

    /* select PLL as system clock */
    RCU_CFG0 &= ~RCU_CFG0_SCS;
    RCU_CFG0 |= RCU_CKSYSSRC_PLL;

    /* wait until PLL is selected as system clock */
    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
        timeout++;
        if (timeout > HXTAL_STARTUP_TIMEOUT)
        {
//            GTK_LOG_ASSERT(GTK_DBG_DRV_RTC, "RTC error %d", __LINE__);
//            GTK_ASSERT(0);
        }
        timeout = 0;
    }
}