SOC设计之分频器

偶数分频：(占空比50%)
偶数N分频比较简单，设定计数器，计数值达到N/2-1时翻转，即可得N分频

module fre_div_even
#(
parameter CNT_WIDTH = 32'd 5, //计数器位宽
parameter DIV_NUM = 32'd 4   //分频数
	)
(
input clk,   
input rstn, 
output reg Data,  
output reg [CNT_WIDTH-1:0] CNT
	);

always @(posedge clk or posedge rstn) 
begin
	if (!rstn) 
		begin
		CNT <= 0;	// reset
		Data <= 0;	
		end
	else if (CNT < DIV_NUM/2-1)
		begin
		CNT <= CNT + 1'b1;	
		end
	else 
		begin
		CNT <= 0;
		Data <= ~Data;
		end
end

endmodule

tb:

奇数分频：(50%占空比 )
奇数N分频设置两个clk_a/clk_b,分别对clk正边沿/负边沿跳转，设定两个计数器分别在（N-1）/2和N-1跳转得Data_a/Data_b，最后将两个相或即可得Data
ps:!-逻辑取反  ~按位取反

module fre_div_odd
#(
parameter CNT_WIDTH = 32'd10,
parameter DIV_NUM = 32'd5
    )
(
input clk,
input rstn,
output Data,
output clk_a,
output clk_b,
output CNT_a,
output CNT_b
    );
reg clk_a;
reg clk_b;
reg [CNT_WIDTH-1:0] CNT_a = 0;
reg [CNT_WIDTH-1:0] CNT_b = 0;


//clk_a cnt
always@(posedge clk or negedge rstn)
begin
     if(!rstn)  CNT_a <= 0;
     else
        begin
        if(CNT_a == DIV_NUM-1)  CNT_a <= 0;
        else CNT_a <=  CNT_a +1;
        end
end

always@(posedge clk or negedge rstn)
begin
     if(!rstn)  clk_a <= 0;
     else
        begin
        if(CNT_a == (DIV_NUM-1)/2 )  clk_a <= !clk_a;
        else if (CNT_a == DIV_NUM-1 ) clk_a <= !clk_a;
        end
end        
     
//clk_b cnt
always@(negedge clk or negedge rstn)
begin
     if(!rstn)  CNT_b <= 0;
      else
        begin
        if(CNT_b == DIV_NUM-1)  CNT_b <= 0;
        else CNT_b <=  CNT_b +1;
        end
end  

always@(negedge clk or negedge rstn)
begin
    if(!rstn) clk_b <= 0;
    else 
    begin
         if(CNT_b == (DIV_NUM-1)/2 ) clk_b <= !clk_b;
         else if (CNT_b == DIV_NUM-1 ) clk_b <= !clk_b;
    end
end      
        
assign Data = clk_a | clk_b;
    
endmodule

tb:

小数分频：
小数分频一般通过先设计两个不同分频比（A/B）的整数分频器，然后控制两个分频器出现的次数(C/D)实现所需的小数分频值
分频比可表示为N=P/Q,其中N表示目标小数分频值，P表示输入脉冲数，P=AC+BD,Q表示输出脉冲数，Q=C+D