verilog实现二十位二进制数转BCD码

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程序

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2019/07/19 14:58:44
// Design Name: 
// Module Name: Bin2BCD
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module Bin2BCD(
	input	wire							clk						,
	input	wire							rst						,
	input	wire	[19:0]					din						,//20λ2½øÖÆÊý¾Ý£¨Ã»ÓиºÊý£©
	//input	wire 							din_valid				,//Êý¾ÝÓÐЧ
	output	reg 	[3:0]					unit_dout				,//¸öλ
	output	reg		[3:0]					tens_dout				,//ʮλ
	output	reg		[3:0]					hund_dout				,//°Ùλ
	output	reg		[3:0]					thou_dout				,//ǧλ
	output	reg		[3:0]					tent_dout				,//Íòλ
	output	reg		[3:0]					hunt_dout				,//Ê®Íò
	output	reg		[3:0]					mill_dout				,//°ÙÍòλ
	output	wire							dout_valid				
    );
	reg [3:0] unit = 4'd0;
	reg [3:0] tens = 4'd0;
	reg [3:0] hund = 4'd0;
	reg [3:0] thou = 4'd0;
	reg [3:0] tent = 4'd0;
	reg [3:0] hunt = 4'd0;
	reg [3:0] mill = 4'd0;
		reg [7:0] cnt;
	reg din_r;
	always @(posedge clk)
	begin
		if(rst| dout_valid) begin
			unit_dout	<=	4'd0;
		    tens_dout	<=	4'd0;
		    hund_dout	<=	4'd0;
		    thou_dout	<=	4'd0;
		    tent_dout	<=	4'd0;
		    hunt_dout	<=	4'd0;
		    mill_dout	<=	4'd0;
		end
		else begin
			unit_dout	<=	{unit[2:0],din_r};
		    tens_dout	<=	{tens[2:0],unit[3]};
		    hund_dout	<=	{hund[2:0],tens[3]};
		    thou_dout	<=	{thou[2:0],hund[3]};
		    tent_dout	<=	{tent[2:0],thou[3]};
		    hunt_dout	<=	{hunt[2:0],tent[3]};
		    mill_dout	<=	{mill[2:0],hunt[3]};
		end
	end
	
	always @(posedge clk) 
	begin
		din_r <= din[19-cnt];
	end
	

	always @(*)
	begin
		if(rst | dout_valid) begin
			unit = 4'd0 ;
			tens = 4'd0 ;
			hund = 4'd0 ;
			thou = 4'd0 ;
			tent = 4'd0 ;
			hunt = 4'd0 ;
		    mill = 4'd0 ;
		end
		else begin
			unit = (unit_dout >	4'd4)	?	unit_dout + 4'd3 : unit_dout;
			tens = (tens_dout >	4'd4)	?	tens_dout + 4'd3 : tens_dout;
			hund = (hund_dout >	4'd4)	?	hund_dout + 4'd3 : hund_dout;
			thou = (thou_dout >	4'd4)	?	thou_dout + 4'd3 : thou_dout;
			tent = (tent_dout >	4'd4)	?	tent_dout + 4'd3 : tent_dout;
			hunt = (hunt_dout >	4'd4)	?	hunt_dout + 4'd3 : hunt_dout;
		    mill = (mill_dout >	4'd4)	?	mill_dout + 4'd3 : mill_dout;
		end
	end
	

	
	always @(posedge clk)
	begin
		if(rst  | dout_valid)
			cnt <= 8'd0;
		else if(cnt == 8'd19)
			cnt <= 8'd0;
		else 
			cnt <= cnt + 1'd1;
	end
	wire valid;
	assign valid = (cnt == 8'd19);
	reg valid_r,valid_r_r;
	
	always @(posedge clk)
	begin
		valid_r <= valid;
		valid_r_r <= valid_r;
	end
	assign dout_valid = valid_r_r;
endmodule

测试文件

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2019/07/19 18:28:56
// Design Name: 
// Module Name: Bin2BCD_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//
module Bin2BCD_tb(
    );
	reg	clk,rst;
	initial begin
		rst = 1'd1;
		#20 rst = 1'd0;
	end

	initial begin
		clk = 0;
		forever begin
			#5 clk = !clk; 
		end
	end
	wire	[3:0]	unit_dout	;	
	wire	[3:0]	tens_dout	;	
	wire	[3:0]	hund_dout	;	
	wire	[3:0]	thou_dout	;	
	wire	[3:0]	tent_dout	;	
	wire	[3:0]	hunt_dout	;	
	wire	[3:0]	mill_dout	;	
	wire			dout_valid  ;
	wire 	[19:0] din = 20'd10020;
	Bin2BCD Bin2BCD_u0(
		.clk			(clk				),	
		.rst			(rst				),	
		.din			(din				),	
		.unit_dout		(unit_dout		    ),
		.tens_dout		(tens_dout		    ),
		.hund_dout		(hund_dout		    ),
		.thou_dout		(thou_dout		    ),
		.tent_dout		(tent_dout		    ),
		.hunt_dout		(hunt_dout		    ),
		.mill_dout		(mill_dout		    ),
		.dout_valid     (dout_valid      	)
	);
endmodule