hdlbits_Exams/review2015_fsmseq

https://hdlbits.01xz.net/wiki/Exams/review2015_fsmseq

用LFSR 写更简单一些

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);

    reg [3:0] d;
    
    always @(posedge clk)
        begin
            d<= {d[2:0],data}; 
            if (reset)
                begin
                start_shifting<=1'b0;
            	d <= 4'b0;
                end
            else if ({d[2:0],data} == 4'b1101)
                start_shifting<=1'b1;
        end
    
    
endmodule