FPGA实现奇数5分频

module Fre_Devide(
		 input			clk,
		 input			rst_n,
		 output reg  	led
);
reg[5:0] clk_cnt;
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n)
		clk_cnt <= 6'd0;
	else if(clk_cnt == 6'd49)
		clk_cnt <= 6'd0;
	else
		clk_cnt <= clk_cnt + 1'b1;
end

always @ (posedge clk or negedge rst_n) begin
	if(!rst_n)
		led <= 1'b0;
	else if(clk_cnt <= 6'd24)
		led <= 1'b1;
	else
		led <= 1'b0;
end
endmodule