testbench 数组整理

去掉前三行和后两列

`timescale 1ns / 1ps


// Company: 
// Engineer:
//
// Create Date:   19:34:30 09/12/2016
// Design Name:   top_module
// Module Name:   D:/SIFT/project/tb_Gaussian_gray/tp_top_test.v
// Project Name:  tb_Gaussian_gray
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: top_module
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 


module tp_top_test;

	parameter size = 4096;
	// Inputs
	reg CLK;
	reg nRESET;
//	reg [7:0] PIXEL_IN;
//	reg VALID_IN;

	// Outputs
	reg [7:0] data_out;
	
	reg [7:0]image_b[0:size-1];
	
	integer read_image_point;
	integer image_point;
	
	reg [12:0] write_addr;
	integer write_text_point;

	// Instantiate the Unit Under Test (UUT)
//	top_module uut (
//		.CLK(CLK), 
//		.nRESET(nRESET), 
//		.PIXEL_IN(PIXEL_IN), 
//		.VALID_IN(VALID_IN), 
//		.PIXEL_OUT(PIXEL_OUT)
//	);

	initial begin
		// Initialize Inputs
		CLK = 0;
		nRESET = 0;
		
		read_image_point = $fopen("pic64.raw","rb+");
		image_point = $fread(image_b,read_image_point);
		
		write_addr = 0;
		write_text_point = $fopen("pic_t.txt","wb+");
		

		// Wait 100 ns for global reset to finish
		#10;
		nRESET = 1;
        
		// Add stimulus here

	end
	
	initial begin
		forever begin
			#5 CLK = ~CLK;
		end
	end
	
	integer m,n;
	
	always@(posedge CLK)
	begin
		for(m=2;m<=63;m=m+1)  //行
			for(n=0;n<=61;n=n+1)  //列
			begin
				write_addr = 64 * m + n;
				data_out = image_b[write_addr];
				$fwrite(write_text_point,"%D",data_out);
				$fwrite(write_text_point,",");
			end
			
			$fclose(write_text_point);
	end
      
endmodule