选择使用TTBR0或TTBR1做为translation table base地址寄存器

当一个TLB miss, VMSA必须进行一个translation table walk,因此必须找到translation table的基地址来进行查找页表。TTBR寄存器保存着这个地址，如下图所描述的：

 Intermediate Physical Address (IPA)

In a translation regime that provides two stages of address translation, the IPA is the address after

the stage 1 translation, and is the input address for the stage 2 translation.

In a translation regime that provides only one stage of address translation, the IPA is identical to the

PA.

In ARM VMSA implementations, only one stage of address translation is provided:

•  if the implementation does not include the Virtualization Extensions
•  when executing in Secure state
•  when executing in Hyp mode.

IPA只在芯片实现virtualization extension时才有意义，对于A9没有意义，IPA与PA是一样的。

并且在A9中MVA与VA是一样的意思。

对于Secure or Non-secure PL1&0 translation table walks:

• TTBR0能被配置去描述全部地址空间映射的translation。或只用来描述低的一部分地址空间的映射。
• 如果TTBR0被配置做为低的一部分地址空间的映射，那么TTBR1就被配置做为高地址空间的内存映射。

TTBCR适当的copy的内容决定了是否地址映射被分成了两部分并且是在哪个地址分的。

Example B3-1 Example use of TTBR0 and TTBR1

An example of using the two TTBRs is:

1、TTBR0

Used for process-specific addresses.Each process maintains a separate first-level translation table. 

On a context switch:

TTBR0 is updated to point to the first-level translation table for the new context

TTBCR is updated if this change changes the size of the translation table

the CONTEXTIDR is updated.
TTBCR can be programmed so that all translations use TTBR0 in a manner compatible with
architecture versions before ARMv6.
2、TTBR1

Used for operating system and I/O addresses, that do not change on a context switch.

如上所说，两套translation tables能被定义做为每一个PL1&0 stage 1 translation所用，TTBR0和TTBR1保存这两套表的base地址。当使用short-descriptor translation table format,TTBCR.N位（决定了是TTBR0还是TTBR1保存了请求translation的translation table base address）暗示了输入VA的最大有效位的数字，

• 如果N == 0那么use TTBR0. 设置TTBCR.N 为0会disable使用第二套translation tables.
• 如果N > 0那么：

--   如果输入的VA的bits[31:32-N]是0那么使用TTBR0

--    否则用TTBR1

下表是TTBCR的N位与如何决定TTBR0还是TTBR1映射空间的对应关系：

TTBCR.N	First address translated with TTBR1	TTBR0 table Size	TTBR0 table entry内Index range
0b000	TTBR1 not used	16kb	VA[31:20]
0b001	0x80000000	8kB	VA[30:20]
0b010	0x40000000	4kb	VA[29:20]
0b011	0x20000000	2kb	VA[28:20]
0b100	0x10000000	1kb	VA[27:20]
0b101	0x08000000	512bytes	VA[26:20]
0b110	0x04000000	256bytes	VA[25:20]
0b111	0x02000000	128bytes	VA[24:20]

   只要TTBCR.N不为0,那么被TTBR1寻址的translation table 的size都是16KB.

How TTBCR.N controls the boundary between the TTBRs, Short-descriptor format

In the selected TTBR. the following bits define the memory region attributes for the translation table walk:

• the RGN, S and C bits, in an implementation that does not include the Multiprocessing Extensions
• the RGN, S, and IRGN[1:0] bits, in an implementation that includes the Multiprocessing Extensions.

 

TTBCR:

 

PD1, bit[5], in an implementation that includes the Security Extensions

Translation table walk disable for translations using TTBR1. This bit controls whether a translation

table walk is performed on a TLB miss, for an address that is translated using TTBR1. The encoding

of this bit is:

0 Perform translation table walks using TTBR1.

1 A TLB miss on an address that is translated using TTBR1 generates a Translation fault.

No translation table walk is performed.

PD0, bit[4], in an implementation that includes the Security Extensions

Translation table walk disable for translations using TTBR0. This bit controls whether a translation

table walk is performed on a TLB miss for an address that is translated using TTBR0. The meanings

of the possible values of this bit are equivalent to those for the PD1 bit.

N, bits[2:0]

Indicate the width of the base address held in TTBR0. In TTBR0, the base address field is

bits[31:14-N]. The value of N also determines:

? whether TTBR0 or TTBR1 is used as the base address for translation table walks.

? the size of the translation table pointed to by TTBR0.

N can take any value from 0 to 7, that is, from 0b000 to 0b111 .