JK触发器

module cy4(input J,
           input K,
		   input clk,
		   input rst_n,
		   output reg Q
		);
always @(posedge clk or negedge rst_n)
  if(!rst_n) Q <= 1'b0;
  else 
    case({J,K})
	  2'b00: Q <= Q;
	  2'b01: Q <= 0;
	  2'b10: Q <= 1;
	  2'b11: Q <= ~Q;
	endcase

endmodule
测试脚本代码：
`timescale 1 ns/ 1 ps
module cy4_vlg_tst();

reg J;
reg K;
reg clk;
reg rst_n;
wire Q;
cy4 i1 (
.J(J),
.K(K),
.Q(Q),
.clk(clk),
.rst_n(rst_n)
);
initial
begin
clk = 0;
rst_n = 1;
#10;
J = 0;
K = 0;
#10;
J = 0;
K = 1;
#10;
J = 1;
K = 0;
#10;
J = 1;
K = 1;
#10;
$stop;
$display(“Running testbench”);
end
always #10 clk = ~clk;
endmodule