[Solaris内存管理]页表格式

PDE and PTE (32bit, 4-Kbyte pages)



PDE (32 bit, 4-MByte pages)



CR4.PAE = 1.
Page Size: 4KB/2MB
Linear Address is still 32bit
Paging table entries are increased to 64bits. Entry numbers decreased from 1024 to 512.
Page-Directory-Pointer Table is added.




How to access 64GByte:
Only 4GBytes is allowed to be accessed at one time
Additional 4GB sections of physical memory can be addressed in either of two way:
Change the pointer in register CR3 to point to another page-directory-pointer table, which in turn points to another set of page directories and page tables.
Change entries in the page-directory-pointer table to point to other page directories, which in turn point to other sets of page tables.



CR4.PAE should be set to 0. PSE-36 CPUID feature flag should be set
Page size: 4MB only








First implementation: 48 bits linear address  40 bits physical address
Potentially: 64 bits linear address  52 bits physical address
PML4 (page map level 4) is added on top of the page directory pointer table
PML4 (9bits) + PDP (9bits) + PDE (9bits) + PTE (9bits) + page offset (12bits)  48 bits linear address
CR4.PAE must be set to 1 before activating IA-32e
Otherwise, general-protection exception #GP.
Page Size: 4KB/2MB