Verilog HDL 第一次实验

1、设计一个键值显示电路，以DE2板上10个拨动开关(switch)作为输入，代表0-9十个十进制数，用七段数码管显示对应的数值。

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module showin7segment(in, seg);

input [9:0] in;

output [6:0] seg;

reg [6:0] seg;

always@ (in)

begin

// seg = {g,f,e,d,c,b,a};

// 0 is on and 1 is off

if (in[9]) seg <= 7'h90;//9

else  if (in[8]) seg <= 7'h80;//8

else  if (in[7]) seg <= 7'hF8;//7

else  if (in[6]) seg <= 7'h82;//6

else  if (in[5]) seg <= 7'h92;//5

else  if (in[4]) seg <= 7'h99;//4

else  if (in[3]) seg <= 7'hB0;//3

else  if (in[2]) seg <= 7'hA4;//2

else  if (in[1]) seg <= 7'hF9;//1

else seg <= 7'hC0;//0

end

endmodule

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2、设计一个流水灯电路，显示方式如下：8个LED先向左依次点亮，循环往复，每个灯亮的持续时间为1秒左右。

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module liushuideng(led,clk);

output[7:0] led;

input clk;

reg[8:0] led_r;

reg[25:0] buffer;//中间变量buffer定义为寄存器型

initial

begin led_r=9'b000000001;buffer=0;end

always @(posedge clk)

begin

if(buffer==26'd250)//判别buffer数值为50 000 000时，做输出处理

begin buffer=0;

led_r <= led_r << 1;

if(led_r == 9'd0)

led_r <= 9'b000000001;

end

else buffer=buffer+1;

end

assign led = led_r[7:0];

endmodule

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