some ideas on FPGA design

(1) judge odd or even  by LSB of a vector,

such as , A[3:0] = 4'b0010, A[0]=0 so A is an even num.

B[3:0] =4'b0011, B[0]=1, so B is an odd num.

 

(2) detect an even by compare pre- and current signal


1  always @( posedge  clk)
2 
3  begin
4 
5          Pre_Field     <=     Field;
6           if ({Pre_Field,Field} == 2 ' b10)
7          Start         <=      1 ' b1; 
8 
9  end  

(3)图像做rotation

(1)左右mirror 可以用片内RAM实现,写数据从0~MAXADDR,  读数据从MAXADDR-addr ~ 0;参考例程DE2_CCD

(2)上下mirror则需要片外 sdram,整帧读写。

 

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