PowerPC简单了解
PowerPC相对于ARM优势:
Powerpc芯片凭借其出色的性能和高度整合和技术先进特性在网络通信应用，工业控制应用，家用数字化，网络存储领域，军工领域,电力系统控制等都具有非常广泛的应用．由于PowerPC相对ARM器件来说价格稍贵，另外ARM开
发工具盗版到处都是，所以在中国目前来说PowerPC不是很普及．但在一些欧美国家应用很广泛的，高校通信专业里面不学PowerPC，应该是高校一个重要失策．个人觉得PowerPC相对ARM优势有下面几点说明， 一是，整合度高
以及技术先进性，现在Freescale PowerPC 处理器集成USB,PCI,DDR控制器，SATA控制器，千兆网口控制器，CAN控制器，RapidIO以及PCI_Express控制器，IEEE1588通信协议，支持各种通信协议CPM协处理器 ，DMA,SPI，I
２C.UART等，客户无须设计复杂的外围电路，减少设计复杂程度以及物料使用，ARM这点比不上 二是，芯片可选范围大，性能高，升级容易，从５０M-1.7G都有处理器，而且POwerPC将象多核处理器发展，如已经推出集成双
e500 core MPC8572,MIPS性能高达６８９７，ARM我看频率是１G的都没有，ARM 大概是 1.1 MIPS/MHz，Power Architecture 是大于2.0MIPS/MHz，所以PowerPC在高端嵌入式应用，占有很大比例，ARM这点比不上，三是,开
发难度方面，其实PowerPC处理器开发难度并不是很高，只不过因为开发的人少，所以中文资料相对较少，另外开发工具也不象ARM那么多盗版的，所以总有些人抱怨PowerPC处理器开发难度大，如Freescale都免费给客户提供
Datasheet,设计详细文档给用户，而且最底层驱动，Freesclae都已经开发好．你可以在他们论坛上提问，或者发邮件给技术支持，他们很快都能回复的, 相信以后用的人会越来越多 四是，价格方面，总有人抱怨说PowerPC处
理器价格贵，相对ARM来说，同样频率的，可能会贵点，但是如果是MIPS/MHz性能比较以及整合的外围电路来说，PowerPC还是有一定优势的，Freescale也意识到这个问题，所以推出了象工作频率低点的MPC8313,MPO8323等低
价格处理器，另外如coldfire也推出低价格处理器，随着Freescale后面产品继续推出，PowerPC处理器价格会越来越便宜
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PowerPC Memory Management Model (MMU)
The MMU specifications are largely provided by the OEA. The primary functions of the MMU are to
translate logical (effective) addresses to physical addresses for memory accesses and I/O accesses (most
I/O accesses are assumed to be memory-mapped), and to provide access protection on a block or page
basis. Note that many aspects of memory management are implementation-dependent. The description in
Chapter 7, “Memory Management,” describes the conceptual model of a MMU; however, processors may
differ in the specific hardware used to implement the MMU model.
Processors require address translation for two types of transactions—instruction accesses and data
accesses to memory (typically generated by load and store instructions).
The memory management specification includes models for 32-bit implementations. The MMU of a 32-bit
processor provides 232 bytes of logical address space accessible to supervisor and user programs with a
4-Kbyte page size and 256-Mbyte segment size.
In 32-bit implementations, the entire 4-Gbyte memory space is defined by sixteen 256-Mbyte segments.
Segments are configured through the 16 segment registers.
The block address translation (BAT) mechanism maps large blocks of memory. Block sizes range from
128 Kbytes to 256 Mbytes and are software-selectable. In addition, the MMU of 32-bit processors uses an
interim virtual address (52 bits) and hashed page tables in the generation of 32-bit physical addresses.
Two types of processor-generated accesses require address translation: instruction accesses and data
accesses to memory generated by load and store instructions. The address translation mechanism is
defined in terms of segment tables (or segment registers in 32-bit implementations) and page tables used
to locate the logical-to-physical address mapping for instruction and data accesses. The segment
information translates the logical address to an interim virtual address, and the page table information
translates the virtual address to a physical address.
Translation lookaside buffers (TLBs) are commonly implemented to keep recently-used page table entries
on-chip. Although their exact characteristics are not specified by the architecture, the general concepts that
are pertinent to the system software are described.
The block address translation (BAT) mechanism is a software-controlled array that stores the available
block address translations on chip. BAT array entries are implemented as pairs of BAT registers that are
accessible as supervisor SPRs; refer to Chapter 7, “Memory Management,” for more information.
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PowerPC Interrupt Model
The interrupt mechanism, defined by the OEA, allows the processor to change to supervisor state as a
result of external signals, errors, or unusual conditions arising in the execution of instructions. When
interrupts occur, information about the state of the processor is saved to various registers and the processor
begins execution at an address (interrupt vector) predetermined for each type of interrupt. Interrupt handler
routines begin execution in supervisor mode. The interrupt model is described in detail in Chapter 6,
“Interrupts.” Note also that some aspects regarding interrupt conditions are defined at other levels of the
architecture. For example, floating-point exception conditions are defined by the UISA, whereas the
interrupt mechanism is defined by the OEA.
The architecture requires that interrupts be handled in program order (excluding the optional floating-point
imprecise modes and the reset and machine check interrupt); therefore, although a particular
implementation may recognize interrupt conditions out of order, they are handled strictly in order. When
an instruction-caused interrupt is recognized, any unexecuted instructions that appear earlier in the
instruction stream, including any that have not yet begun to execute, are required to complete before the
interrupt is taken. Any interrupts caused by those instructions must be handled first. Likewise, interrupts
that are asynchronous and precise are recognized when they occur, but are not handled until all instructions
currently executing successfully complete processing and report their results.
The OEA supports four types of interrupts:
? Synchronous, precise
? Synchronous, imprecise
? Asynchronous, maskable
? Asynchronous, nonmaskable