IA-32 Concept

一 Concept
1. Operating Mode: The IA-32 architecture supports three operating modes and one quasi-operating mode: Protected mode, Real-address mode, System management mode (SMM) and Virtual-8086 mode.

Note: PE flag in control register CR0 controls whether the processor is operating in real-address or protected mode.

2. Memory Model
Flat Model: memory appears to a program as a single, continuous address space, called a linear address space. Code (a program’s instructions), data, and the procedure stack are all contained in this address space.
Segmented Model: code, data, and stacks are typically contained in separate segments
Real-Address: The real-address mode uses a specific implementation of segmented memory in which the linear address space for the program and the operating system/executive consists of an array of segments of up to 64 KBytes in size each.

3. Operating Mode vs. Memory Model
Protected mode: the processor can use any of the memory models described in this section. (The real-addressing mode memory model is ordinarily used only when the processor is in the virtual-8086 mode.)
Real-address mode: When in real-address mode, the processor only supports the realaddress
mode memory model.

4. Address
Physical address: the address processor addresses on its bus.
Linear address: a 4G single, continuous space address .
Logical address: consists of a segment selector and an offset.

二. Basic execution environment
In protected mode, all memory accesses pass through either the global descriptor table (GDT) or the (optional) local descriptor table (LDT),

1. Registers
General-Purpose Registers(EAX, EBX... 32-bit)
Control Registers(CR0, CR1...32-bit)
Segment Registers(DS, CS... 16-bit): Hold 16bit segment selector
Memory management registers(GDTR, LDTR, IDTR, TR 48bit)

2. Data Structures
Segment Descriptor: provides the base address of a segment and access rights, type, and usage information
Segment Selector: provides an index into the GDT or LDT (to its associated segment descriptor), a global/local flag (that determines whether the segment selector points to the GDT or the LDT), and access rights information.
System Segment: the task-state segment(TSS) and the LDT.
Gate: provide protected gateways to system procedures and handlers that operate at different privilege levels than application programs and procedures.

Note: The GDT and IDT are not considered a segment because it is not accessed by means of a segment selector and segment descriptor.

Page Direcotry Entry and Page Table Entry all contain the "physical address" of a page(Because they are used to tranlate Linear Address, they can not use Linear Address)

When writing application code, programmers generally create segment selectors with assembler directives and symbols. The assembler and other tools then create the actual segment selector values associated with these directives and symbols. If writing system code, programmers may need to create segment selectors directly.   

When using the flat (unsegmented) memory model, the segment registers are loaded with segment selectors that point to overlapping segments, each of which begins at address 0 of the linear address space

3. 32-Bit vs. 16-Bit Address and Operand Sizes

32-bit address and operand sizes: the maximum linear address or segment offset is FFFFFFFFH, and operand sizes are typically 8 bits or 32 bits.
16-bit address and operand sizes: the maximum linear address or segment offset is FFFFH (216-1), and operand sizes are typically 8 bits or 16 bits.

When using 32-bit addressing, a logical address (or far pointer) consists of a 16-bit segment selector and a 32-bit offset; when using 16-bit addressing, it consists of a 16-bit segment selector and a 16-bit offset.

When operating in protected mode, the segment descriptor for the currently executing code segment defines the default address and operand size.