Vivado 蜂鸟 e203 MCU200T/DDR200T 添加MIG IP DDR3控制器 RISC-V

更新一下，之前内容有错误
参考链接

FPGA上外挂DDR2&DDR3&MIG IP的使用记录
https://www.cnblogs.com/kingstacker/p/9444409.html

【分享】 利用蜂鸟E203搭建SoC【4】——DDR200T内存扩展
https://www.rvmcu.com/community-topic-id-744.html

DDR200T中DDR的使用与时序介绍
https://www.rvmcu.com/community-topic-id-822.html

【分享】 小白也能学会的DDR存储拓展教程【2021 hbirdv2最新版】
https://www.rvmcu.com/community-topic-id-843.html

VIVADO MIG核添加列表之外的DDR型号
https://blog.csdn.net/neufeifatonju/article/details/104915776

DATASHEET-MT41K128M16JT-125

http://www.elecfans.com/p/xc-2500277248.html

1. 新建工程后新建IP-Memory Interface Generator

2.选择DDR3 SDRAM

3. 新建Memory Part：自定义参数生成型号MT41K128M16JT-125

更改参数参考以下：
参考MT41K128M16JT-125K手册的更改

tcke

tfaw

tras

trcd

trefi

trfc

trp

trtp

twtr

4.设置Memory Options与FPGA Options

这里的频率设置，要根据内核的处理频率倒退过来，需要按需设置，还要加mmcm输出所需时钟信号。

5. ODT

6.【关键】对照ddr200t设置IO引脚

参考ddr200t产品手册
https://www.nucleisys.com/upload/files/fpga/doc/Nuclei_FPGA_DebugKit_Intro_20211018.pdf
对比这添加引脚信息


等等。。

这里我提供我自己做好的ucf文件，直接复制到txt里，另存为为ddr3.ucf

NET   "ddr3_addr[0]"                           LOC = "AA4"   |    ;
NET   "ddr3_addr[10]"                          LOC = "Y1"    |    ;
NET   "ddr3_addr[11]"                          LOC = "W2"    |    ;
NET   "ddr3_addr[12]"                          LOC = "Y2"    |    ;
NET   "ddr3_addr[13]"                          LOC = "U1"    |    ;
NET   "ddr3_addr[1]"                           LOC = "AB2"   |    ;
NET   "ddr3_addr[2]"                           LOC = "AA5"   |    ;
NET   "ddr3_addr[3]"                           LOC = "AB5"   |    ;
NET   "ddr3_addr[4]"                           LOC = "AB1"   |    ;
NET   "ddr3_addr[5]"                           LOC = "U3"    |    ;
NET   "ddr3_addr[6]"                           LOC = "W1"    |    ;
NET   "ddr3_addr[7]"                           LOC = "T1"    |    ;
NET   "ddr3_addr[8]"                           LOC = "V2"    |    ;
NET   "ddr3_addr[9]"                           LOC = "U2"    |    ;
NET   "ddr3_ba[0]"                             LOC = "AA3"   |    ;
NET   "ddr3_ba[1]"                             LOC = "Y3"    |    ;
NET   "ddr3_ba[2]"                             LOC = "Y4"    |    ;
NET   "ddr3_cas_n"                             LOC = "W4"    |    ;
NET   "ddr3_ck_n[0]"                           LOC = "R2"    |    ;
NET   "ddr3_ck_p[0]"                           LOC = "R3"    |    ;
NET   "ddr3_cke[0]"                            LOC = "T5"    |    ;
NET   "ddr3_cs_n[0]"                           LOC = "AB3"   |    ;
NET   "ddr3_dm[0]"                             LOC = "D2"    |    ;
NET   "ddr3_dm[1]"                             LOC = "G2"    |    ;
NET   "ddr3_dq[0]"                             LOC = "C2"    |    ;
NET   "ddr3_dq[10]"                            LOC = "H2"    |    ;
NET   "ddr3_dq[11]"                            LOC = "H5"    |    ;
NET   "ddr3_dq[12]"                            LOC = "J1"    |    ;
NET   "ddr3_dq[13]"                            LOC = "J5"    |    ;
NET   "ddr3_dq[14]"                            LOC = "K1"    |    ;
NET   "ddr3_dq[15]"                            LOC = "H4"    |    ;
NET   "ddr3_dq[1]"                             LOC = "G1"    |    ;
NET   "ddr3_dq[2]"                             LOC = "A1"    |    ;
NET   "ddr3_dq[3]"                             LOC = "F3"    |    ;
NET   "ddr3_dq[4]"                             LOC = "B2"    |    ;
NET   "ddr3_dq[5]"                             LOC = "F1"    |    ;
NET   "ddr3_dq[6]"                             LOC = "B1"    |    ;
NET   "ddr3_dq[7]"                             LOC = "E2"    |    ;
NET   "ddr3_dq[8]"                             LOC = "H3"    |    ;
NET   "ddr3_dq[9]"                             LOC = "G3"    |    ;
NET   "ddr3_dqs_n[0]"                          LOC = "D1"    |    ;
NET   "ddr3_dqs_n[1]"                          LOC = "J2"    |    ;
NET   "ddr3_dqs_p[0]"                          LOC = "E1"    |    ;
NET   "ddr3_dqs_p[1]"                          LOC = "K2"    |    ;
NET   "ddr3_odt[0]"                            LOC = "U5"    |    ;
NET   "ddr3_ras_n"                             LOC = "V4"    |    ;
NET   "ddr3_reset_n"                           LOC = "W6"    |    ;
NET   "ddr3_we_n"                              LOC = "AA1"   |    ;

7.其他设置，一直next就行

8.生成中

9.配置icb2axi总线，利用block design设置链路

。。。未完待续