imx6ull设备树

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1 设备树 imx6ull.dtsi

2  设备树 imx6ull-bsp.dts


1 设备树 imx6ull.dtsi

/*
 * Copyright 2015-2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include 
#include 
#include 
#include "imx6ull-pinfunc.h"
#include "imx6ull-pinfunc-snvs.h"
#include "skeleton.dtsi"

/ {
	aliases {
		can0 = &flexcan1;
		can1 = &flexcan2;
		ethernet0 = &fec1;
		ethernet1 = &fec2;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		serial6 = &uart7;
		serial7 = &uart8;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &ecspi3;
		spi3 = &ecspi4;
		usbphy0 = &usbphy1;
		usbphy1 = &usbphy2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			clock-latency = <61036>; /* two CLK32 periods */
			operating-points = <
				/* kHz	uV */
				996000	1275000
				792000	1225000
				528000	1175000
				396000	1025000
				198000	950000
			>;
			fsl,soc-operating-points = <
				/* KHz	uV */
				996000	1175000
				792000	1175000
				528000	1175000
				396000	1175000
				198000	1175000
			>;
			fsl,low-power-run;
			clocks = <&clks IMX6UL_CLK_ARM>,
				 <&clks IMX6UL_CLK_PLL2_BUS>,
				 <&clks IMX6UL_CLK_PLL2_PFD2>,
				 <&clks IMX6UL_CA7_SECONDARY_SEL>,
				 <&clks IMX6UL_CLK_STEP>,
				 <&clks IMX6UL_CLK_PLL1_SW>,
				 <&clks IMX6UL_CLK_PLL1_SYS>,
				 <&clks IMX6UL_PLL1_BYPASS>,
				 <&clks IMX6UL_CLK_PLL1>,
				 <&clks IMX6UL_PLL1_BYPASS_SRC>,
				 <&clks IMX6UL_CLK_OSC>;
			clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m", "secondary_sel", "step",
				      "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc";
		};
	};

	intc: interrupt-controller@00a01000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00a01000 0x1000>,
		      <0x00a02000 0x100>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil: clock@0 {
			compatible = "fixed-clock";
			reg = <0>;
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "ckil";
		};

		osc: clock@1 {
			compatible = "fixed-clock";
			reg = <1>;
			#clock-cells = <0>;
			clock-frequency = <24000000>;
			clock-output-names = "osc";
		};

		ipp_di0: clock@2 {
			compatible = "fixed-clock";
			reg = <2>;
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "ipp_di0";
		};

		ipp_di1: clock@3 {
			compatible = "fixed-clock";
			reg = <3>;
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "ipp_di1";
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gpc>;
		ranges;

		busfreq {
			compatible = "fsl,imx_busfreq";
			clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>,
				 <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>,
				 <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>,
				 <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>,
				 <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>,
				 <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>,
				 <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>,
				 <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>,
				 <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>,
				 <&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>,
				 <&clks IMX6UL_CLK_PLL1>;
			clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
				      "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
				      "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
				      "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
			fsl,max_ddr_freq = <400000000>;
		};

		pmu {
			compatible = "arm,cortex-a7-pmu";
			interrupts = ;
			status = "disabled";
		};

		ocrams: sram@00900000 {
			compatible = "fsl,lpm-sram";
			reg = <0x00900000 0x4000>;
		};

		ocrams_ddr: sram@00904000 {
			compatible = "fsl,ddr-lpm-sram";
			reg = <0x00904000 0x1000>;
		};

		ocram: sram@00905000 {
			compatible = "mmio-sram";
			reg = <0x00905000 0x1B000>;
		};

		dma_apbh: dma-apbh@01804000 {
			compatible = "fsl,imx6ul-dma-apbh", "fsl,imx28-dma-apbh";
			reg = <0x01804000 0x2000>;
			interrupts = ,
				     ,
				     ,
				     ;
			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
			#dma-cells = <1>;
			dma-channels = <4>;
			clocks = <&clks IMX6UL_CLK_APBHDMA>;
		};

		gpmi: gpmi-nand@01806000{
			compatible = "fsl,imx6ull-gpmi-nand", "fsl, imx6ul-gpmi-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
			reg-names = "gpmi-nand", "bch";
			interrupts = ;
			interrupt-names = "bch";
			clocks = <&clks IMX6UL_CLK_GPMI_IO>,
				 <&clks IMX6UL_CLK_GPMI_APB>,
				 <&clks IMX6UL_CLK_GPMI_BCH>,
				 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
				 <&clks IMX6UL_CLK_PER_BCH>;
			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
				      "gpmi_bch_apb", "per1_bch";
			dmas = <&dma_apbh 0>;
			dma-names = "rx-tx";
			status = "disabled";
		};

		aips1: aips-bus@02000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02000000 0x100000>;
			ranges;

			spba-bus@02000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x02000000 0x40000>;
				ranges;

				spdif: spdif@02004000 {
					compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif";
					reg = <0x02004000 0x4000>;
					interrupts = ;
					dmas = <&sdma 41 18 0>,
					       <&sdma 42 18 0>;
					dma-names = "rx", "tx";
					clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>,
						 <&clks IMX6UL_CLK_OSC>,
						 <&clks IMX6UL_CLK_SPDIF>,
						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
						 <&clks IMX6UL_CLK_IPG>,
						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
						 <&clks IMX6UL_CLK_SPBA>;
					clock-names = "core", "rxtx0",
						      "rxtx1", "rxtx2",
						      "rxtx3", "rxtx4",
						      "rxtx5", "rxtx6",
						      "rxtx7", "dma";
					status = "disabled";
				};

				ecspi1: ecspi@02008000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
					reg = <0x02008000 0x4000>;
					interrupts = ;
					clocks = <&clks IMX6UL_CLK_ECSPI1>,
						 <&clks IMX6UL_CLK_ECSPI1>;
					clock-names = "ipg", "per";
					dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi2: ecspi@0200c000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
					reg = <0x0200c000 0x4000>;
					interrupts = ;
					clocks = <&clks IMX6UL_CLK_ECSPI2>,
						 <&clks IMX6UL_CLK_ECSPI2>;
					clock-names = "ipg", "per";
					dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi3: ecspi@02010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
					reg = <0x02010000 0x4000>;
					interrupts = ;
					clocks = <&clks IMX6UL_CLK_ECSPI3>,
						 <&clks IMX6UL_CLK_ECSPI3>;
					clock-names = "ipg", "per";
					dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi4: ecspi@02014000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
					reg = <0x02014000 0x4000>;
					interrupts = ;
					clocks = <&clks IMX6UL_CLK_ECSPI4>,
						 <&clks IMX6UL_CLK_ECSPI4>;
					clock-names = "ipg", "per";
					dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart7: serial@02018000 {
					compatible = "fsl,imx6ul-uart",
						     "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02018000 0x4000>;
					interrupts = ;
					clocks = <&clks IMX6UL_CLK_UART7_IPG>,
						 <&clks IMX6UL_CLK_UART7_SERIAL>;
					clock-names = "ipg", "per";
					dmas = <&sdma 43 4 0>, <&sdma 44 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart1: serial@02020000 {
					compatible = "fsl,imx6ul-uart",
						     "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02020000 0x4000>;
					interrupts = ;
					clocks = <&clks IMX6UL_CLK_UART1_IPG>,
						 <&clks IMX6UL_CLK_UART1_SERIAL>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				esai: esai@02024000 {
					compatible = "fsl,imx6ull-esai";
					reg = <0x02024000 0x4000>;
					interrupts = ;
					clocks = <&clks IMX6UL_CLK_ESAI_IPG>,
						 <&clks IMX6UL_CLK_ESAI_MEM>,
						 <&clks IMX6UL_CLK_ESAI_EXTAL>,
						 <&clks IMX6UL_CLK_ESAI_IPG>,
						 <&clks IMX6UL_CLK_SPBA>;
					clock-names = "core", "mem", "extal",
						      "fsys", "dma";
					dmas = <&sdma 0 21 0>, <&sdma 47 21 0>;
					dma-names = "rx", "tx";
					dma-source = <&gpr 0 14 0 15>;
					status = "disabled";
				};

				sai1: sai@02028000 {
					compatible = "fsl,imx6ul-sai",
						     "fsl,imx6sx-sai";
					reg = <0x02028000 0x4000>;
					interrupts = ;
					clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
						 <&clks IMX6UL_CLK_DUMMY>,
						 <&clks IMX6UL_CLK_SAI1>,
						 <&clks 0>, <&clks 0>;
					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
					dma-names = "rx", "tx";
					dmas = <&sdma 35 24 0>, <&sdma 36 24 0>;
					status = "disabled";
				};

				sai2: sai@0202c000 {
					compatible = "fsl,imx6ul-sai",
						     "fsl,imx6sx-sai";
					reg = <0x0202c000 0x4000>;
					interrupts = ;
					clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
						 <&clks IMX6UL_CLK_DUMMY>,
						 <&clks IMX6UL_CLK_SAI2>,
						 <&clks 0>, <&clks 0>;
					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
					dma-names = "rx", "tx";
					dmas = <&sdma 37 24 0>, <&sdma 38 24 0>;
					status = "disabled";
				};

				sai3: sai@02030000 {
					compatible = "fsl,imx6ul-sai",
						     "fsl,imx6sx-sai";
					reg = <0x02030000 0x4000>;
					interrupts = ;
					clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
						 <&clks IMX6UL_CLK_DUMMY>,
						 <&clks IMX6UL_CLK_SAI3>,
						 <&clks 0>, <&clks 0>;
					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
					dma-names = "rx", "tx";
					dmas = <&sdma 39 24 0>, <&sdma 40 24 0>;
					status = "disabled";
				};

				asrc: asrc@02034000 {
					compatible = "fsl,imx53-asrc";
					reg = <0x02034000 0x4000>;
					interrupts = ;
					clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
						<&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
						<&clks IMX6UL_CLK_SPBA>;
					clock-names = "mem", "ipg", "asrck_0",
						"asrck_1", "asrck_2", "asrck_3", "asrck_4",
						"asrck_5", "asrck_6", "asrck_7", "asrck_8",
						"asrck_9", "asrck_a", "asrck_b", "asrck_c",
						"asrck_d", "asrck_e", "asrck_f", "dma";
					dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
						<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
					dma-names = "rxa", "rxb", "rxc",
						    "txa", "txb", "txc";
					fsl,asrc-rate  = <48000>;
					fsl,asrc-width = <16>;
					status = "okay";
				};
			};

			tsc: tsc@02040000 {
				compatible = "fsl,imx6ul-tsc";
				reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
				interrupts = ,
					     ;
				clocks = <&clks IMX6UL_CLK_IPG>,
					 <&clks IMX6UL_CLK_ADC2>;
				clock-names = "tsc", "adc";
				status = "disabled";
			};

			pwm1: pwm@02080000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x02080000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_PWM1>,
					 <&clks IMX6UL_CLK_PWM1>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm2: pwm@02084000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x02084000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm3: pwm@02088000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x02088000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_PWM3>,
					 <&clks IMX6UL_CLK_PWM3>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm4: pwm@0208c000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x0208c000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			flexcan1: can@02090000 {
				compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
				reg = <0x02090000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
					 <&clks IMX6UL_CLK_CAN1_SERIAL>;
				clock-names = "ipg", "per";
				stop-mode = <&gpr 0x10 1 0x10 17>;
				status = "disabled";
			};

			flexcan2: can@02094000 {
				compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
				reg = <0x02094000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
					 <&clks IMX6UL_CLK_CAN2_SERIAL>;
				clock-names = "ipg", "per";
				stop-mode = <&gpr 0x10 2 0x10 18>;
				status = "disabled";
			};

			gpt1: gpt@02098000 {
				compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt";
				reg = <0x02098000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
					 <&clks IMX6UL_CLK_GPT_3M>;
				clock-names = "ipg", "osc_per";
			};

			gpio1: gpio@0209c000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x0209c000 0x4000>;
				interrupts = ,
					     ;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@020a0000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x020a0000 0x4000>;
				interrupts = ,
					     ;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@020a4000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x020a4000 0x4000>;
				interrupts = ,
					     ;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@020a8000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x020a8000 0x4000>;
				interrupts = ,
					     ;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio5: gpio@020ac000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x020ac000 0x4000>;
				interrupts = ,
					     ;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			snvslp: snvs@020b0000 {
				compatible = "fsl,imx6ul-snvs";
				reg = <0x020b0000 0x4000>;
				interrupts = ;
			};

			fec2: ethernet@020b4000 {
				compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
				reg = <0x020b4000 0x4000>;
				interrupts = ,
					     ;
				clocks = <&clks IMX6UL_CLK_ENET>,
					 <&clks IMX6UL_CLK_ENET_AHB>,
					 <&clks IMX6UL_CLK_ENET_PTP>,
					 <&clks IMX6UL_CLK_ENET2_REF_125M>,
					 <&clks IMX6UL_CLK_ENET2_REF_125M>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				stop-mode = <&gpr 0x10 4>;
				fsl,num-tx-queues=<1>;
				fsl,num-rx-queues=<1>;
				fsl,magic-packet;
				fsl,wakeup_irq = <0>;
				status = "disabled";
			};

			kpp: kpp@020b8000 {
				compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
				reg = <0x020b8000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_DUMMY>;
				status = "disabled";
			};

			wdog1: wdog@020bc000 {
				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
				reg = <0x020bc000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_WDOG1>;
			};

			wdog2: wdog@020c0000 {
				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
				reg = <0x020c0000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_WDOG2>;
				status = "disabled";
			};

			clks: ccm@020c4000 {
				compatible = "fsl,imx6ul-ccm";
				reg = <0x020c4000 0x4000>;
				interrupts = ,
					     ;
				#clock-cells = <1>;
				clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
				clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
			};

			anatop: anatop@020c8000 {
				compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
					     "syscon", "simple-bus";
				reg = <0x020c8000 0x1000>;
				interrupts = ,
					     ,
					     ;

				reg_3p0: regulator-3p0@120 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd3p0";
					regulator-min-microvolt = <2625000>;
					regulator-max-microvolt = <3400000>;
					anatop-reg-offset = <0x120>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
					anatop-min-voltage = <2625000>;
					anatop-max-voltage = <3400000>;
					anatop-enable-bit = <0>;
				};

				reg_arm: regulator-vddcore@140 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "cpu";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <0>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <24>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				reg_soc: regulator-vddsoc@140 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddsoc";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <18>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <28>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};
			};

			usbphy1: usbphy@020c9000 {
				compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
				reg = <0x020c9000 0x1000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_USBPHY1>;
				phy-3p0-supply = <®_3p0>;
				fsl,anatop = <&anatop>;
			};

			usbphy2: usbphy@020ca000 {
				compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
				reg = <0x020ca000 0x1000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_USBPHY2>;
				phy-3p0-supply = <®_3p0>;
				fsl,anatop = <&anatop>;
			};

			tempmon: tempmon {
				compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
				interrupts = ;
				fsl,tempmon = <&anatop>;
				fsl,tempmon-data = <&ocotp>;
				clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
			};

			snvs: snvs@020cc000 {
				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
				reg = <0x020cc000 0x4000>;

				snvs_rtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap = <&snvs>;
					offset = <0x34>;
					interrupts = , ;
				};

				snvs_poweroff: snvs-poweroff {
					compatible = "syscon-poweroff";
					regmap = <&snvs>;
					offset = <0x38>;
					mask = <0x61>;
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = ;
					linux,keycode = ;
					wakeup;
				};
			};

			epit1: epit@020d0000 {
				reg = <0x020d0000 0x4000>;
				interrupts = ;
			};

			epit2: epit@020d4000 {
				reg = <0x020d4000 0x4000>;
				interrupts = ;
			};

			src: src@020d8000 {
				compatible = "fsl,imx6ul-src", "fsl,imx51-src";
				reg = <0x020d8000 0x4000>;
				interrupts = ,
					     ;
				#reset-cells = <1>;
			};

			gpc: gpc@020dc000 {
				compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
				reg = <0x020dc000 0x4000>;
				interrupt-controller;
				#interrupt-cells = <3>;
				interrupts = ;
				interrupt-parent = <&intc>;
				fsl,mf-mix-wakeup-irq = <0xfc00000 0x7d00 0x0 0x1400640>;
			};

			iomuxc: iomuxc@020e0000 {
				compatible = "fsl,imx6ul-iomuxc";
				reg = <0x020e0000 0x4000>;
			};

			gpr: iomuxc-gpr@020e4000 {
				compatible = "fsl,imx6ul-iomuxc-gpr",
					"fsl,imx6q-iomuxc-gpr", "syscon";
				reg = <0x020e4000 0x4000>;
			};

			mqs: mqs {
				compatible = "fsl,imx6sx-mqs";
				gpr = <&gpr>;
				status = "disabled";
			};

			gpt2: gpt@020e8000 {
				compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt";
				reg = <0x020e8000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "ipg", "per";
			};

			sdma: sdma@020ec000 {
				compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma";
				reg = <0x020ec000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_SDMA>,
					 <&clks IMX6UL_CLK_SDMA>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				iram = <&ocram>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
			};

			pwm5: pwm@020f0000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x020f0000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm6: pwm@020f4000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x020f4000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm7: pwm@020f8000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x020f8000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm8: pwm@020fc000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x020fc000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};
		};

		aips2: aips-bus@02100000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02100000 0x100000>;
			ranges;

			usbotg1: usb@02184000 {
				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
				reg = <0x02184000 0x200>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_USBOH3>;
				fsl,usbphy = <&usbphy1>;
				fsl,usbmisc = <&usbmisc 0>;
				fsl,anatop = <&anatop>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbotg2: usb@02184200 {
				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
				reg = <0x02184200 0x200>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_USBOH3>;
				fsl,usbphy = <&usbphy2>;
				fsl,usbmisc = <&usbmisc 1>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbmisc: usbmisc@02184800 {
				#index-cells = <1>;
				compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
				reg = <0x02184800 0x200>;
			};

			fec1: ethernet@02188000 {
				compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
				reg = <0x02188000 0x4000>;
				interrupts = ,
					     ;
				clocks = <&clks IMX6UL_CLK_ENET>,
					 <&clks IMX6UL_CLK_ENET_AHB>,
					 <&clks IMX6UL_CLK_ENET_PTP>,
					 <&clks IMX6UL_CLK_ENET_REF>,
					 <&clks IMX6UL_CLK_ENET_REF>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				stop-mode = <&gpr 0x10 3>;
				fsl,num-tx-queues=<1>;
				fsl,num-rx-queues=<1>;
				fsl,magic-packet;
				fsl,wakeup_irq = <0>;
				status = "disabled";
                        };

			usdhc1: usdhc@02190000 {
				compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
				reg = <0x02190000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_USDHC1>,
					 <&clks IMX6UL_CLK_USDHC1>,
					 <&clks IMX6UL_CLK_USDHC1>;
				clock-names = "ipg", "ahb", "per";
				assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
				assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
				assigned-clock-rates = <0>, <132000000>;
				bus-width = <4>;
				fsl,tuning-step= <2>;
				status = "disabled";
			};

			usdhc2: usdhc@02194000 {
				compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
				reg = <0x02194000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_USDHC2>,
					 <&clks IMX6UL_CLK_USDHC2>,
					 <&clks IMX6UL_CLK_USDHC2>;
				clock-names = "ipg", "ahb", "per";
				assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
				assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
				assigned-clock-rates = <0>, <132000000>;
				bus-width = <4>;
				fsl,tuning-step= <2>;
				status = "disabled";
			};

			adc1: adc@02198000 {
				compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
				reg = <0x02198000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_ADC1>;
				num-channels = <2>;
				clock-names = "adc";
				status = "disabled";
                        };

			i2c1: i2c@021a0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
				reg = <0x021a0000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_I2C1>;
				status = "disabled";
			};

			i2c2: i2c@021a4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
				reg = <0x021a4000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_I2C2>;
				status = "disabled";
			};

			i2c3: i2c@021a8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
				reg = <0x021a8000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_I2C3>;
				status = "disabled";
			};

			romcp@021ac000 {
				compatible = "fsl,imx6ul-romcp", "syscon";
				reg = <0x021ac000 0x4000>;
			};

			mmdc: mmdc@021b0000 {
				compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
				reg = <0x021b0000 0x4000>;
			};

			weim: weim@021b8000 {
				compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
				reg = <0x021b8000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_DUMMY>;
			};

			ocotp: ocotp-ctrl@021bc000 {
				compatible = "fsl,imx6ull-ocotp", "syscon";
				reg = <0x021bc000 0x4000>;
				clocks = <&clks IMX6UL_CLK_OCOTP>;
			};

			csu: csu@021c0000 {
				compatible = "fsl,imx6ul-csu";
				reg = <0x021c0000 0x4000>;
				interrupts = ;
				status = "disabled";
			};

			csi: csi@021c4000 {
				compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi";
				reg = <0x021c4000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					<&clks IMX6UL_CLK_CSI>,
					<&clks IMX6UL_CLK_DUMMY>;
				clock-names = "disp-axi", "csi_mclk", "disp_dcic";
				status = "disabled";
			};

			lcdif: lcdif@021c8000 {
				compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
				reg = <0x021c8000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
					 <&clks IMX6UL_CLK_LCDIF_APB>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "pix", "axi", "disp_axi";
				status = "disabled";
			};

			pxp: pxp@021cc000 {
				compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
				reg = <0x021cc000 0x4000>;
				interrupts = ,
					;
				clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>;
				clock-names = "pxp_ipg", "pxp_axi";
				status = "disabled";
			};

			qspi: qspi@021e0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ull-qspi", "fsl,imx6ul-qspi";
				reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_QSPI>,
					 <&clks IMX6UL_CLK_QSPI>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			uart2: serial@021e8000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021e8000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_UART2_IPG>,
					 <&clks IMX6UL_CLK_UART2_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart3: serial@021ec000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021ec000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_UART3_IPG>,
					 <&clks IMX6UL_CLK_UART3_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart4: serial@021f0000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021f0000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_UART4_IPG>,
					 <&clks IMX6UL_CLK_UART4_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart5: serial@021f4000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021f4000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_UART5_IPG>,
					 <&clks IMX6UL_CLK_UART5_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			i2c4: i2c@021f8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
				reg = <0x021f8000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_I2C4>;
				status = "disabled";
			};

			uart6: serial@021fc000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021fc000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_UART6_IPG>,
					 <&clks IMX6UL_CLK_UART6_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};
		};

		aips3: aips-bus@02200000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02200000 0x100000>;
			ranges;

			dcp: dcp@02280000 {
				compatible = "fsl,imx6sl-dcp";
				reg = <0x02280000 0x4000>;
				interrupts = ,
					     ,
					     ;
				clocks = <&clks IMX6UL_CLK_DCP_CLK>;
				clock-names = "dcp";
			};

			rngb: rngb@02284000 {
				compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng";
				reg = <0x02284000 0x4000>;
				interrupts = ;
				clocks =  <&clks IMX6UL_CLK_DUMMY>;
			};

			uart8: serial@02288000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x02288000 0x4000>;
				interrupts = ;
				clocks = <&clks IMX6UL_CLK_UART8_IPG>,
					 <&clks IMX6UL_CLK_UART8_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 45 4 0>, <&sdma 46 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			epdc: epdc@0228c000 {
				compatible = "fsl,imx7d-epdc";
				interrupts = ;
				reg = <0x0228c000 0x4000>;
				clocks = <&clks IMX6UL_CLK_EPDC_ACLK>,
					 <&clks IMX6UL_CLK_EPDC_PIX>;
				clock-names = "epdc_axi", "epdc_pix";
				/* Need to fix epdc-ram */
				/* epdc-ram = <&gpr 0x4 30>; */
				status = "disabled";
			};

			iomuxc_snvs: iomuxc-snvs@02290000 {
				compatible = "fsl,imx6ull-iomuxc-snvs";
				reg = <0x02290000 0x10000>;
			};

			snvs_gpr: snvs-gpr@0x02294000 {
				compatible = "fsl, imx6ull-snvs-gpr";
				reg = <0x02294000 0x10000>;
			};
		};
	};
};

2  设备树 imx6ull-bsp.dts

/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */


#include 
#include "imx6ull.dtsi"

/ {
	model = "Freescale i.MX6 ULL 14x14 EVK Board";
	compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";

	chosen {
		stdout-path = &uart1;
	};

	memory {
		reg = <0x80000000 0x20000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x8000000>;
			linux,cma-default;
		};
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm1 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <7>;
		status = "okay";
	};

	pxp_v4l2 {
		compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
		status = "okay";
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_can_3v3: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "can-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
		};

		reg_sd1_vmmc: regulator@1 {
			compatible = "regulator-fixed";
			regulator-name = "VSD_3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			/* gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; */
			enable-active-high;
		};

		reg_gpio_dvfs: regulator-gpio {
			compatible = "regulator-gpio";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_dvfs>;
			regulator-min-microvolt = <1300000>;
			regulator-max-microvolt = <1400000>;
			regulator-name = "gpio_dvfs";
			regulator-type = "voltage";
			gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
			states = <1300000 0x1 1400000 0x0>;
		};
	};

	74hc595{
		compatible = "seg_74hc595";
		pinctrl-names="pinctrl_74hc595";
		gpio_sck = <&gpio5 10 GPIO_ACTIVE_LOW>;
		gpio_dio = <&gpio5 11 GPIO_ACTIVE_LOW>;
		gpio_rck = <&gpio5 7 GPIO_ACTIVE_LOW>;
	};

	ultra_sonic{
		compatible = "ultra_sonic";
		pinctrl-names="pinctrl_ultra_sonic";
		gpio_trigger=<&gpio1 18 GPIO_ACTIVE_LOW>;
		//gpio_pulse=<&gpio1 18 GPIO_ACTIVE_LOW>;

		interrupt-parent = <&gpio1>;
		interrupts = <18 IRQ_TYPE_EDGE_BOTH>; /* FALLING RISING */
		status = "okay";
	};

	gpio {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds
					 &pinctrl_gpio_motor
					 &pinctrl_gpio_power
					 &pinctrl_gpio>;

		sys-led{
			label = "sys-led";
			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
			default-state = "on";
		};

		led2{
			label = "led2";
			gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		motor{
			label = "motor";
			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		power{
			label = "power";
			gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
		gpio1{
			label = "gpio1";
			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};
		gpio2{
			label = "gpio2";
			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};
	};

	gpio_keys: gpio_keys@0 {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;
		#address-cells = <1>;
		#size-cells = <0>;
		autorepeat;
		/*
		key@1 {
			label = "USER-KEY1";
			linux,code = <114>;
			gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
			gpio-key,wakeup;
		};
		*/

		key@2 {
			label = "USER-KEY2";
			linux,code = <115>;
			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
			gpio-key,wakeup;
		};
	};

	sound {
		compatible = "fsl,imx6ul-evk-wm8960",
			   "fsl,imx-audio-wm8960";
		model = "wm8960-audio";
		cpu-dai = <&sai2>;
		audio-codec = <&codec>;
		asrc-controller = <&asrc>;
		codec-master;
		gpr = <&gpr 4 0x100000 0x100000>;
		/*
                 * hp-det = ;
		 * hp-det-pin: JD1 JD2  or JD3
		 * hp-det-polarity = 0: hp detect high for headphone
		 * hp-det-polarity = 1: hp detect high for speaker
		 */
		hp-det = <3 0>;
		/* hp-det-gpios = <&gpio5 4 0>;
		   mic-det-gpios = <&gpio5 4 0>; */
		audio-routing =
			"Headphone Jack", "HP_L",
			"Headphone Jack", "HP_R",
			"Ext Spk", "SPK_LP",
			"Ext Spk", "SPK_LN",
			"Ext Spk", "SPK_RP",
			"Ext Spk", "SPK_RN",
			"LINPUT2", "Mic Jack",
			"LINPUT3", "Mic Jack",
			"RINPUT1", "Main MIC",
			"RINPUT2", "Main MIC",
			"Mic Jack", "MICB",
			"Main MIC", "MICB",
			"CPU-Playback", "ASRC-Playback",
			"Playback", "CPU-Playback",
			"ASRC-Capture", "CPU-Capture",
			"CPU-Capture", "Capture";
	};

	spi4 {
		compatible = "spi-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_spi4>;
		pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
		status = "disabled";
		gpio-sck = <&gpio5 11 0>;
		gpio-mosi = <&gpio5 10 0>;
		cs-gpios = <&gpio5 7 0>;
		num-chipselects = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		gpio_spi: gpio_spi@0 {
			compatible = "fairchild,74hc595";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0>;
			registers-number = <1>;
			registers-default = /bits/ 8 <0x57>;
			spi-max-frequency = <100000>;
		};
	};

       sii902x_reset: sii902x-reset {
                compatible = "gpio-reset";
                reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
                reset-delay-us = <100000>;
                #reset-cells = <0>;
                status = "disabled";
        };
};

&adc1{

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc>;
	num-channels = <3>;
	status ="okay";
};

&cpu0 {
	arm-supply = <®_arm>;
	soc-supply = <®_soc>;
	dc-supply = <®_gpio_dvfs>;
};

&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <722534400>;
};

&csi {
	status = "okay";

	port {
		csi1_ep: endpoint {
			remote-endpoint = <&ov5640_ep>;
		};
	};
};
/*
&ecspi3 {
        fsl,spi-num-chipselects = <1>;
        cs-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_ecspi3>;
        status = "disable";
	

	spidev: icm20608@0 {
	compatible = "alientek,icm20608";
        spi-max-frequency = <8000000>;
        reg = <0>;
    };
	
};
*/
/*
&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1
		     &pinctrl_fec1_reset>;
	phy-mode = "rmii";
	phy-handle = <ðphy0>;
	phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <200>;
	status = "okay";
};
*/
&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2
		     &pinctrl_fec2_reset>;
	phy-mode = "rmii";
	phy-handle = <ðphy1>;
	phy-reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <200>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <®_can_3v3>;
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <®_can_3v3>;
	status = "disabled";
};

&gpc {
	fsl,cpu_pupscr_sw2iso = <0x1>;
	fsl,cpu_pupscr_sw = <0x0>;
	fsl,cpu_pdnscr_iso2sw = <0x1>;
	fsl,cpu_pdnscr_iso = <0x1>;
	fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
	/*
	mag3110@0e {
		compatible = "fsl,mag3110";
		reg = <0x0e>;
		position = <2>;
		status = "disable";
	};
	
	ap3216c@1e {
		//compatible = "ap3216c";
		compatible = "LiteOn,ap3216c";
		reg = <0x1e>;
		status = "disable";
	};
	*/

	mpu6050@68 {
		compatible = "mpu6050";
		reg = <0x68>;
		status = "okay";
	};

	bmp280@76 {
		compatible = "bmp280";
		reg = <0x76>;//0x76
		status = "okay";
	};
	
	ssd1306@3c{
		compatible = "ssd1306";
		reg = <0x3c>;//0x78
		status = "okay";
	};
	
};

&i2c2 {
	clock_frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	codec: wm8960@1a {
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		clocks = <&clks IMX6UL_CLK_SAI2>;
		clock-names = "mclk";
		wlf,shared-lrclk;
	};
	
	ov5640: ov5640@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_csi1
			     &csi_pwn_rst>;
		clocks = <&clks IMX6UL_CLK_CSI>;
		clock-names = "csi_mclk";
		pwn-gpios = <&gpio1 4 1>;
		rst-gpios = <&gpio1 2 0>;
		csi_id = <0>;
		mclk = <24000000>;
		mclk_source = <0>;
		status = "disable";
		port {
			ov5640_ep: endpoint {
				remote-endpoint = <&csi1_ep>;
			};
		};
	};
	/*

    edt-ft5x06@38 {
		compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
		pinctrl-names = "default";
		pinctrl-0 = <&ts_int_pin
			     &ts_reset_pin>;

		reg = <0x38>;
		interrupt-parent = <&gpio1>;
		interrupts = <9 0>;
		reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
		irq-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
		status = "disabled";
	};

        goodix_ts@5d {
		compatible = "goodix,gt9xx";
		reg = <0x5d>;
		status = "disabled";
		interrupt-parent = <&gpio1>;
		interrupts = <9 0>;
		pinctrl-0 = <&ts_int_pin
				    &ts_reset_pin>;
		goodix,rst-gpio = <&gpio5 9  GPIO_ACTIVE_LOW>;
		goodix,irq-gpio = <&gpio1 9  GPIO_ACTIVE_LOW>;
	};

    sii902x: sii902x@39 {
		compatible = "SiI,sii902x";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_sii902x>;
		interrupt-parent = <&gpio1>;
		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
		irq-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
		mode_str = "1280x720M@60";
		bits-per-pixel = <16>;
		resets = <&sii902x_reset>;
		reg = <0x39>;
		status = "disabled";
    };
	*/
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_1>;
	imx6ul-evk {
		pinctrl_hog_1: hoggrp-1 {
			fsl,pins = <
				MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059 /* SD1 CD */
				MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059 /* SD1 VSELECT */
				MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x13058 /* USB_OTG1_ID */
			>;
		};

		pinctrl_csi1: csi1grp {
			fsl,pins = <
				MX6UL_PAD_CSI_MCLK__CSI_MCLK		0x1b008
				MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK	0x1b008
				MX6UL_PAD_CSI_VSYNC__CSI_VSYNC		0x1b008
				MX6UL_PAD_CSI_HSYNC__CSI_HSYNC		0x1b008
				MX6UL_PAD_CSI_DATA00__CSI_DATA02	0x1b008
				MX6UL_PAD_CSI_DATA01__CSI_DATA03	0x1b008
				MX6UL_PAD_CSI_DATA02__CSI_DATA04	0x1b008
				MX6UL_PAD_CSI_DATA03__CSI_DATA05	0x1b008
				MX6UL_PAD_CSI_DATA04__CSI_DATA06	0x1b008
				MX6UL_PAD_CSI_DATA05__CSI_DATA07	0x1b008
				MX6UL_PAD_CSI_DATA06__CSI_DATA08	0x1b008
				MX6UL_PAD_CSI_DATA07__CSI_DATA09	0x1b008
			>;
		};

		pinctrl_enet1: enet1grp {
			fsl,pins = <
				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001B009
			>;
		};

		pinctrl_enet2: enet2grp {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
				MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
				MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
				MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
				MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
				MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
				MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
				MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
				MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
				MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001B009
			>;
		};

		pinctrl_ecspi3: ecspi3grp {
				fsl,pins = <
						//MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO        0x100b1  /* MISO*/
						//MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI        0x100b1  /* MOSI*/
						//MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK      0x100b1  /* CLK*/
						//MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSIMX6UL_PAD_UART2_TX_DATA__GPIO1_IO20       0x100b0  /* CS*/
				>;
		};

		pinctrl_gpio_leds: gpio-leds {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x17059
				MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17059
			>;
		};
	
		pinctrl_gpio_motor: gpio-motor {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0x17059
			>;
		};

		pinctrl_gpio_power: gpio-power {
			fsl,pins = <
				MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x17059
			>;
		};

		pinctrl_gpio: pinctrl_gpio {
			fsl,pins = <
				MX6UL_PAD_UART2_RTS_B__GPIO1_IO23	0x17059
				MX6UL_PAD_UART2_CTS_B__GPIO1_IO22	0x17059
			>;
		};

		pinctrl_adc: gpio-adc {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
			>;
		};


		pinctrl_gpio_keys: gpio-keys {
			fsl,pins = <
				//MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x80000000
				MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0x80000000
			>;

		};
		pinctrl_ultra_sonic: ultra_sonic {
			fsl,pins = <
				MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x80000000
			>;

		};

		pinctrl_flexcan1: flexcan1grp{
			fsl,pins = <
				MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
				MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
			>;
		};

		pinctrl_flexcan2: flexcan2grp{
			fsl,pins = <
				//MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
				//MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
				MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
				MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
			>;
		};

		pinctrl_lcdif_dat: lcdifdatgrp {
			fsl,pins = <
				MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x49
				MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x49
				MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x49
				MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x49
				MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x49
				MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x49
				MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x49
				MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x51
				MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x49
				MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x49
				MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x49
				MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x49
				MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x49
				MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x49
				MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x49
				MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x51
				MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x49
				MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x49
				MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x49
				MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x49
				MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x49
				MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x49
				MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x49
				MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x51
			>;
		};

		pinctrl_lcdif_ctrl: lcdifctrlgrp {
			fsl,pins = <
				MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x49
				MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x49
				MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x49
				MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x49
			>;
		};

		pinctrl_pwm1: pwm1grp {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
			>;
		};

		pinctrl_qspi: qspigrp {
			fsl,pins = <
				MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
				MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
				MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
				MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
				MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
				MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
			>;
		};

		pinctrl_sai2: sai2grp {
			fsl,pins = <
				MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
				MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
				MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
				MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
				MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
			>;
		};

		pinctrl_sii902x: hdmigrp-1 {
				fsl,pins = <
						MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x11
				>;
		};

		pinctrl_tsc: tscgrp {
			fsl,pins = <
				//MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
				//MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
				//MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
				//MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
				MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
				MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
				//MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x1b0b1
				//MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x1b0b1
			>;
		};

		pinctrl_uart2dte: uart2dtegrp {
			fsl,pins = <
				//MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX	0x1b0b1
				//MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX	0x1b0b1
				//MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS	0x1b0b1
				//MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS	0x1b0b1
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b0b1
				MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b1
			>;
		};		

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10071
				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
			>;
		};

		pinctrl_usdhc2_8bit: usdhc2grp_8bit {
			fsl,pins = <
				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
			>;
		};

		pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
			fsl,pins = <
				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
			>;
		};

		pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
			fsl,pins = <
				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
			>;
		};

		pinctrl_wdog: wdoggrp {
			fsl,pins = <
				MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
			>;
		};

		ts_int_pin: ts_int_pin_mux {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO09__GPIO1_IO09	0x49
			>;
		};

		csi_pwn_rst: csi_pwn_rstgrp {
			fsl,pins = <
				//MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0x10b0
				//MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0x10b0
			>;
		};
	};
};

&iomuxc_snvs {
	pinctrl-names = "default_snvs";
        pinctrl-0 = <&pinctrl_hog_2>;
        imx6ul-evk {
		pinctrl_hog_2: hoggrp-2 {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
                        >;
                };

		pinctrl_dvfs: dvfsgrp {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
                        >;
                };
		
		pinctrl_lcdif_reset: lcdifresetgrp {
                        fsl,pins = <
                                /* used for lcd reset */
                                MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x49
                        >;
                };

		pinctrl_spi4: spi4grp {
                        fsl,pins = <
                                //MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10        0x70a1
                                //MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11        0x70a1
                                //MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x70a1
                                //MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x80000000
                        >;
                };

		pinctrl_74hc595:74hc595grp{
			fsl,pins = <
					MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10        0x17059
					MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11		 0x17059
					MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x17059
			>;
		};

		pinctrl_fec1_reset: fec1_resetgrp {
			fsl,pins = <
				//MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x79
			>;
		};

		pinctrl_fec2_reset: fec2_resetgrp {
			fsl,pins = <
				MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x79
			>;
		};

                pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04   0x17059
                        >;
                };

		ts_reset_pin: ts_reset_pin_mux {
			fsl,pins = <
				MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x49
			>;
		};


        };
};


&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat
		     &pinctrl_lcdif_ctrl>;
	display = <&display0>;
	status = "okay";

        display0: display {
                bits-per-pixel = <16>;
                bus-width = <24>;

                display-timings {
                        native-mode = <&timing0>;
                        timing0: timing0 {
                        clock-frequency = <35500000>;
                        hactive = <800>;
                        vactive = <480>;
                        hfront-porch = <210>;
                        hback-porch = <46>;
                        hsync-len = <20>;
                        vback-porch = <23>;
                        vfront-porch = <22>;
                        vsync-len = <3>;

                        hsync-active = <0>;
                        vsync-active = <0>;
                        de-active = <1>;
                        pixelclk-active = <1>;
                        };
                };
        };
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&pxp {
	status = "okay";
};

&qspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	status = "okay";
	ddrsmp=<0>;

	flash0: n25q256a@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q256a";
		spi-max-frequency = <29000000>;
		spi-nor,ddr-quad-read-dummy = <6>;
		reg = <0>;
	};
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2
		     &pinctrl_sai2_hp_det_b>;

	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
			  <&clks IMX6UL_CLK_SAI2>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <0>, <11289600>;

	status = "okay";
};

&tsc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_tsc>;
	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
	measure-delay-time = <0xffff>;
	pre-charge-time = <0xfff>;
	status = "disabled";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	//fsl,uart-has-rtscts;
	/* for DTE mode, add below change */
	/* fsl,dte-mode; */
	/* pinctrl-0 = <&pinctrl_uart2dte>; */
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	srp-disable;
	hnp-disable;
	adp-disable;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usbphy1 {
	tx-d-cal = <0x5>;
};

&usbphy2 {
	tx-d-cal = <0x5>;
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	keep-power-in-suspend;
	enable-sdio-wakeup;
	vmmc-supply = <®_sd1_vmmc>;
	no-1-8-v;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,wdog_b;
};

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