FPGA的串口收发测试的top文件

`timescale 1ns / 1ns
//
// Company:
// Engineer:
//
// Create Date: 13:54:53 10/16/2022
// Design Name:
// Module Name: uart_rx_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module uart_rx_top(
input clk,
input rst_n,
input uart_rx,
output uart_tx
);

wire finish_receive;
wire[7:0] now_rx_data;
reg[7:0] now_tx_data;

localparam IDLE = 0;
localparam SET_Data = 1; //send HELLO ALINX\r\n
localparam SET_Enable = 2; //send HELLO ALINX\r\n
localparam WAIT = 3;

reg tx_data_enable;
wire finish_send;
reg[3:0] state;

reg [7:0] get_data;
reg finish_rx0;
reg finish_rx1;

always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1’b0)
begin
state <= IDLE;
tx_data_enable <= 1’b1;
//count <= 8’d0;
end
else
case(state)
IDLE:
begin
if(finish_reveive_posedge == 1)//已经完成了接收
begin
state <= SET_Data;
tx_data_enable <= 1;
now_tx_data <= now_rx_data +1’b1;
end
else
begin
state <= IDLE;
tx_data_enable <= 1;
//now_tx_data <= 0;
end

		end
		
	SET_Data:
	   begin
			tx_data_enable <= 0;
			state          <= SET_Enable;
	   end
	SET_Enable:
      begin
			 tx_data_enable <= 0;
			 state          <= WAIT;

/// if(finish_send == 1’d0)//等待模组拉低发送完成标志
// state <= WAIT;
// else
// state <=state;

      end
	WAIT:
	    begin
			 if(finish_send == 1'd1)//发送完成
						 begin
                   state <= IDLE;											 
						 end
				 else //当前字节没有发送完成，要等待。
						 begin
								state <= state;
						 end
		 end
     
	
  default : state          <= IDLE;			  
   
endcase

end

always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1’b0)
begin

			finish_rx0    <= 1'b0;
			finish_rx1    <= 1'b0;
		end
else //if(finish_receive == 1'b1)
		begin
			finish_rx0    <= finish_receive;
			finish_rx1    <= finish_rx0;
		end

end

//always@(*)
//begin
// get_data = now_rx_data;
//
//end

assign finish_reveive_posedge = ((finish_rx1 == 1’b0) && (finish_rx0 == 1’b1));

uart_tx my_uart_tx
(
.clk (clk),
.rst_n (rst_n),
.now_tx_data (now_tx_data),
.tx_data_enable (tx_data_enable),
.baud_set (3’d0),
.finish_send (finish_send),
.rs232_tx_pin (uart_tx)

);

uart_rx my_uart_rx(
.clk (clk), //clock input
.rst_n (rst_n), //asynchronous reset input, low active
.baud_set (3’d0), //
.finish_receive (finish_receive), //完成接收
.rs232_rx_pin (uart_rx),
.now_rx_data (now_rx_data)
);

endmodule