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本文根据IC Compiler 1 Lab Guide.pdf而写,一共分为两个部分,Q&A是记录ICC使用中遇到的一些问题,ICC 1 Lab Guide主要是熟练一下整个流程并记录各条命令。实际上,这些命令在每个Lab下的.solution/run.tcl中都有记录。
由于pdf中没有目录,不利于新手理解整个流程,所以本博客的目的就是把整个流程弄成目录的形式,帮助新手理解。如下图,整个设计流程一目了然,还可以很方便的进行跳转。
本博客中还会加入一些名词解释,帮助大家更好地理解各个专有名字的意思以及它们的作用。
后面就基本使用英文来写了吧,锻炼一下自己的英语水平,顺带记一下专有名词,英语很重要哦。
.solutions/run.tcl
.Milkyway_database.pdf
文档。Milkyway database is a unifying design storage format for tools in the Synopsys Galaxy™ Design Platform, including Design Compiler®,IC Compiler™, StarRC™, IC Validator,PrimeRail, and the Milkyway Environment.
Synopsys工具可以访问Milkyway database中设计和库的物理信息。这个物理信息不仅包含库单元的物理和工艺信息,还包含某个特定设计的placement和routing等信息。
Milkyway database是层次化的文件管理架构。但是,为了确保文件一致性和完整性,只能通过Synopsys工具进行访问(open_mw_lib)。
当打开一个设计的Milkyway database时,工具会自动链接到其他所需的reference Milkyway database(参考库)
Milkyway database中信息的基本单位是cell。cell可以是芯片中I / O,standard cell,或者整个芯片的物理版图。在Synopsys工具中,可以使用open_mw_cel命令打开一个当前Milkyway database中的cell进行编辑。
Milkyway database中同一个cell的不同表示形式,称为“views”。
CEL view包含完整的layout信息,FRAM view只包含cell的抽象表示用于placement 和 routing。
IC Compiler和 PrimeRail等工具在执行相应的工作(physical verification、IR drop和electro migrationanalysis)是也会产生相应的views。
Milkyway database除了包含物理库信息、工艺信息,还包含特定设计的物理信息,即保存了placement 和 routing的结果。也就是说,Milkyway database包含了设计库(design library)和参考库(reference libraries)。
create_mw_lib -technology $tech_file -mw_reference_library "$mw_path/sc $mw_path/io $mw_path\
/ram16x128" -bus_naming_style {[%d]} -open $my_mw_lib
#############################################################
# Netlist(verilog format)
# Open Library & Import Designs
import_designs $verilog_file -format verilog -top $top_design
#############################################################
# TLU+
# Set TLU+ files
set_tlu_plus_files -max_tluplus $tlup_max -min_tluplus $tlup_min -tech2itf_map $tlup_map
# Check the physical and logical libraries for consistency
# Recommended complete check, which would include checks related to UDF power constraints,
# multi-corner multi-mode, and CCS current modeling
# set_check_library_options -all
# Default check
check_library
# Check that TLU+ files are attached and that they pass three sanity checks
check_tlu_plus_files
# Verify that the specified link libraries have been loaded
list_libs
# P/G logical connection
# Define the "logical" connections between power/ground pins and nets
source $derive_pg_file
check_mv_design -power_nets
#############################################################
# Constraints
# Apply the top level design constraints
read_sdc $sdc_file
# Check if any key timing constraints (for example clocks, input/output constraints) are missing
check_timing
# Check to see what "timing exception" constraints are applied to your design
report_timing_requirements
# Check to see if timing analysis was disabled along any paths
report_disable_timing
# Check to see if the design has been configured for a specific "mode" or "case", for example "functional" versus "test" mode
report_case_analysis
# Verify that the clocks are appropriately modeled
report_clock
report_clock -skew
#############################################################
# Control
# Apply some timing and optimization controls which are specified in ./scripts/opt_ctrl.tcl
source $ctrl_file
# Run a "zero-interconnect"(zic) timing report
source scripts/zic_timing.tcl
# Remove the ideal network definition so that it will be buffered during physical design
remove_ideal_network [get_ports scan_en]
# Save the cell and notice the new binary files under risc_chip.mw/CEL
save_mw_cel -as RISC_CHIP_data_setup
DEF:(Design exchange format),叫设计交换格式,是ASCII格式的文件,它描述的是实际的设计,对库单元及它们的位置和连接关系进行了列表,使用DEF来在不同的设计系统间传递设计,同时又可以保持设计的内容不变。DEF与只传递几何信息的GDSII不一样。它可以将设计的逻辑信息和物理信息传递给布局布线工具。逻辑信息包括逻辑连接关系(由网表表示)、grouping信息以及物理约束。物理信息包括布局规划、布局位置及方向、绕线几何数据。
# Read in the provided DEF file, the .def file's generation will be discussed in later Units: # Design Planning
read_def $def_file
# Ensure that standard cells will not be placed under the power and ground metal routes(this constraint is not part of DEF)
set_pnet_options -complete {METAL3 METAL4}
# Save the design cell and notice the new binary files under risc_chip.mw/CEL
save_mw_cel -as RISC_CHIP_floorplanned
# Place and optimize the design for timing, and generate a timing report
place_opt
redirect -tee place_opt.timing {report_timing}
# Analyze congestion
report_congestion -grc_based -by_layer -routing_stage global
# Save the design cell
save_mw_cel -as RISC_CHIP_placed
# Remove the "clock uncertainty" and enable hold-time fixing
# Using default settings to generate the clock tree
remove_clock_uncertainty [all_clocks]
set_fix_hold [all_clocks]
clock_opt
redirect -tee clock_opt.timing {report_timing}
# Save the design cell
save_mw_cel -as RISC_CHIP_cts
exit
# Invoke IC Compiler's GUI
icc_shell -gui
# Open Libraries
open_mw_lib $my_mw_lib
open_mw_cel RISC_CHIP_cts
# Re-apply the timing and optimization controls, which were applied during data setup
source $ctrl_file
# Route the design. This will take care of all the signal nets(the clock nets were already detail-routed by clock_opt)
route_opt
# Generate a timing report
view report_timing -nosplit
v rt
# By default timing reports show maximum delay or setup timing
v rt -delay min
# Generate physical design statistics
report_design -physical
# Save the design
save_mw_cel -as RISC_CHIP_routed
# Quit the IC Complier shell
exit or quit
# Invoke IC Compiler and start the GUI
cd lab2_dp
icc_shell -gui
# Open the orca_setup cell from the orca_lib.mv design library
open_mw_cel -library orca_lib.mw orca_setup
# Apply timing and optimization controls which are specified in ./scripts/opt_ctrl.tcl
source script/opt_ctrl.tcl
# Switch to the Design Planning task
gui_set_current_task -name {Design Planning}
# Create the corner and P/G cells and define all pad cell positions using a provided script
# Reason: The logical netlist from synthesis does not contain physical-only cells such as
# power and ground pad cells or corner pad cells. You have to therefore create these extra
# cells before being able to physically place them in the periphery area of your chip.
source -echo scripts/pad_cell_cons.tcl
# Initialize the floorplan, including core utilization and core to left/right/bottom/top spacing
initialize_floorplan -core_utilization 0.8 -left_io2core 30.0 -bottom_io2core 30.0 -right_io2core 30.0 -top_io2core 30.0
# Insert the pad filler
insert_pad_filler -cell "pfeed10000 pfeed05000 pfeed02000 pfeed01000 pfeed00500 pfeed00200 pfeed00100 pfeed00050 pfeed00010 pfeed00005"
# You could also type this
source scripts/insert_pad_filler.tcl
# Make the "logical" connection(no physical routing) between the power/ground signals and all power/ground pins of the I/O pads, macros and standard cells
source -echo scripts/connect_pg.tcl
# Build the PAD area power supply ring
create_pad_rings
# Save the design as "floorplan_init"
save_mw_cel -as floorplan_init
# Manually place the macros in the core area such that their connections to the I/O pads are as short as possible
# To ensure that the three macros are placed as expected, you can source the following script
source -echo scripts/preplace_macros.tcl
# Verify that the current VF placement strategy options have default settings
report_fp_placement_strategy
# Apply a sliver size of 10 to prevent standard cells from being placed in narrow channels(<10um) between macros
set_fp_placement_strategy -sliver_size 10
# Execute a timing-driven VF placement with "no hierarchy gravity"(to ensure that the
# "logical hierarchy" does not affect placement of this non-hierarchical or flat layout)
create_fp_placement -timing_driven -no_hierarchy_gravity
# Examine the global route congestion map
report_congestion -grc_based -by_layer -routing_stage_global
# Apply macro placement constraints to turn some of the macros into arrays. This makes
# more easier in routing power and ground straps and macro rings.
source -echo scripts/macro_place_cons.tcl
# Double check your settings
report_fp_placement_strategy
report_fp_macro_options
# Set a hard keepout margin of 10 microns around all macros.
source -echo scripts/keepout.tcl
# Running the VF placer again
create_fp_placement -timing_driven -no_hierarchy_gravity
# Analyze the global route congestion map again
report_congestion -grc_based -by_layer -routing_stage_global
# Lock down all macros
set_dont_touch_placement [all_macro_cells]
# Save the cell
save_mw_cel -as floorplan_placed
# Create P/G rings around six groups of macros using macro_pg_rings.tcl
# Defining a rough "region" that encompasses a group of macros
# Defining the block ring layers, widths and offsets
# Creating(commiting) the metal routes
source ./script/macro_pg_rings.tcl
# The fixed macro "PLL" in the upper-left corner does not have a P/G ring around it - this
# will be done by PNS
在按照IC Compiler 1 Lab Guide手册学习ICC的时候,遇到了上图所示的问题,解决方法为:关于ICC-200809-SP5 “module is not defined” 原因以及解决办法
将IC_Compiler_2010.12-SP2/ref/mw_lib中的io、ram16x128、sc中的CEL、FRAM、LM中的文件中的_数字
全部命名为:数字
即可,使用命令:rename _ : *
(这个命令不一定全部适用,需要自己改改,参考:linux中mv和rename的区别)。建议直接把压缩包传到虚拟机(工作站)中,然后解压就不会出现这种问题了。
将三个文件夹中的文件名都修改之后,重新执行,便可正常运行。
Please refer to: ICC 中的 FRAM 什么意思?
technology file
is unique to each technology