verilog实现串并转换

串转并：我这个实现为每输入四位串行数据，输出一个并行数据

module c2b(input clk,
           input rst_n,
           input data_i,
           output reg[3:0] data_o);
           
           reg [2:0] cnt;
           always@(posedge clk or negedge rst_n)begin
                if(!rst_n)begin
                    data_o <= 4'b0000;
                    cnt <= 3'b000;
                end
                else begin
                    if(cnt < 4)begin
                        data_o <= {data_o[2:0],data_i};
                        cnt <= cnt + 1;
                    end
                    else begin
                        data_o <= {3'b000,data_i};
                        cnt <= 3'b001;
                    end
                end

            end


endmodule

`timescale 1ns / 1ps

 
 
module sim_s2f_cdc(
 
    );
	
	reg clk;
	reg rst_n;
	reg data_i;
	wire [3:0]data_o;

	
	initial begin
		clk = 0;
		forever
		#2 clk = ~ clk;
	end
	

	
	initial begin
		rst_n = 0;
		data_i = 0;
		
		#10
		rst_n = 1;
		
		#14
		@(posedge clk)
		data_i = 1;
		@(posedge clk)
		data_i = 0;
		@(posedge clk)
        data_i = 1;
        @(posedge clk)
        data_i = 0;
        @(posedge clk)
        data_i = 1;
        @(posedge clk)
        data_i = 1;
         @(posedge clk)
        data_i = 1;
        @(posedge clk)
        data_i = 0;
         @(posedge clk)
        data_i = 1;
        @(posedge clk)
        data_i = 0;
        @(posedge clk)
        data_i = 1;
        @(posedge clk)
        data_i = 1;       
	end
	
	c2b inst_slow2fast(
	.clk(clk),
	.rst_n(rst_n),
	.data_i(data_i),
    .data_o(data_o)	
	);
	
	
	
	
endmodule

串行输入1010,1110,1011仿真结果正确

并串转换：

module b2c(input clk,
           input rst_n,
           input [3:0] data_i,
           output reg data_o);
           

           reg [2:0] cnt;
           
           

           always@(posedge clk or negedge rst_n)begin
                if(!rst_n)begin
                    data_o <= 0;
                    cnt <= 3'b000;
                end
                else begin
                    if(cnt < 4)begin
                        data_o <= data_i[3-cnt];
                        cnt <= cnt + 1;
                    end
                    else begin
                        data_o <= data_i[3];
                        cnt <= 3'b001;
                    end
                end

            end


endmodule

`timescale 1ns / 1ps

 
 
module sim_s2f_cdc(
 
    );
	
	reg clk;
	reg rst_n;
	reg [3:0]data_i;
	wire data_o;

	
	initial begin
		clk = 0;
		forever
		#2 clk = ~ clk;
	end
	

	
	initial begin
		rst_n = 0;
		data_i = 0;
		
		#10
		rst_n = 1;
		
		#14
		@(posedge clk)
		data_i = 4'b1010;
		
		#14
		@(posedge clk)
		data_i = 4'b1110;
		
		#14
		@(posedge clk)
        data_i = 4'b1011;
    
	end
	
	b2c inst_slow2fast(
	.clk(clk),
	.rst_n(rst_n),
	.data_i(data_i),
    .data_o(data_o)	
	);