vcs快速仿真调试demo代码示例

命令：
vcs -full64 -sverilog -R demo_test.sv

demo_test.sv

program demo_test();
initial begin
int a;
bit[31:0] u_a;

u_a = 'hA0A0_FAFA;
a = u_a;
$display("u_a is %0d", u_a);
$display("a is %0d", a);
end
endprogram