vcs仿真器在0时刻的行为

我们在使用vcs仿真器进行仿真时，有时会遇到在0时刻某些always块被触发的情况，分析这些always块是怎么被触发的有助于我们理解仿真器的行为，以及如何避免这些触发。

1、0时刻触发的例子

1.1、rst信号0时刻赋值0

module harness;
    reg rst;

    initial begin
        rst = 0;
        #10 rst = 1;
    end

    always@(posedge rst) begin: always_block1
        $display("The always block1 executed @Time %f", $time());
    end

    always@(negedge rst) begin: always_block2
        $display("The always block2 executed @Time %f", $time());
    end

    always@(rst) begin: always_block3
        $display("The always block3 executed @Time %f", $time());
    end

endmodule

仿真结果：

The always block2 executed @Time 0.000000
The always block3 executed @Time 0.000000
The always block1 executed @Time 10.000000
The always block3 executed @Time 10.000000

1.2、rst信号0时刻赋值1

module harness;
    reg rst;

    initial begin
        rst = 1;
        #10 rst = 0;
    end

    always@(posedge rst) begin: always_block1
        $display("The always block1 executed @Time %f", $time());
    end

    always@(negedge rst) begin: always_block2
        $display("The always block2 executed @Time %f", $time());
    end

    always@(rst) begin: always_block3
        $display("The always block3 executed @Time %f", $time());
    end

endmodule

仿真结果：

The always block1 executed @Time 0.000000
The always block3 executed @Time 0.000000
The always block2 executed @Time 10.000000
The always block3 executed @Time 10.000000

二、vcs手册中的解释

At simulation time 0, VCS executes always blocks where any of the signals in the event control expression that follows the always keyword (the sensitivity list) initializes at time 0.

也就是说，只要你在0时刻对rst信号进行赋值操作，就会触发对应的always块。之前我理解的是0时刻出现了信号的跳变导致触发了对应的always块，现在看来这种认知是不太对的。

在vcs的手册中，还说明了对于其它的仿真器，0时刻的行为可能不是这样的：

With other Verilog simulators, there are two possibilities at time 0:
•The simulator executes the initial block first, initializing reg rst, then the simulator evaluates the event control sensitivity list for the always block and executes the always block because the simulator initialized rst.
•The simulator evaluates the event control sensitivity list for the always block, and so far, reg rst has not changed its value during this time step. Therefore, the simulator does not execute the always block. Then the simulator executes the initial block and initializes rst. When this occurs, the simulator does not re-evaluate the event control sensitivity list for the always block.

三、+vcs+initreg+random特性

该特性可以看成是一种特殊的0时刻赋值操作，即可以当成是一个独立的initial语句，且该语句的执行优先级最高，因此，如果使用+vcs+initreg+random特性，也会在0时刻触发对应的always块。